Datasheet
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009
18
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APPLICATION INFORMATION
Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about
30% at high line with the synchronization scheme facilitated by the UCC3817A. Figure 7 shows the suggested
technique for synchronizing the UCC3817A to the downstream converter. With this technique, maximum ripple
reduction as shown in Figure 6 is achievable. The output capacitance value can be significantly reduced if its
choice is dictated by ripple current or the capacitor life can be increased as a result. In cost sensitive designs
where holdup time is not critical, this is a significant advantage.
Table 1. Effects of Synchronization on Boost Capacitor Current
V
IN
= 85 V V
IN
= 120 V V
IN
= 240 V
D(Q2) Q1/Q2 D1/Q2 Q1/Q2 D1/Q2 Q1/Q2 D1/Q2
0.35 1.491 A 0.835 A 1.341 A 0.663 A 1.024 A 0.731 A
0.45 1.432 A 0.93 A 1.276 A 0.664 A 0.897 A 0.614 A
An alternative method of synchronization to achieve the same ripple reduction is possible. In this method, the
turnon of Q1 is synchronized to the turnoff of Q2. While this method yields almost identical ripple reduction and
maintains trailing edge modulation on both converters, the synchronization is much more difficult to achieve and
the circuit can become susceptible to noise as the synchronizing edge itself is being modulated.
CT
RT
R
T
C
T
D2
D1
C1
Gate Drive
From Down
Stream PWM
UCC3817A
Figure 7. Synchronizing the UCC3817A to a Down-Stream Converter