Datasheet

 
 

SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009
10
www.ti.com
APPLICATION INFORMATION
Power switch selection:
As in any power supply design, tradeoffs between performance, cost and size have
to be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch
for several different devices at the switching frequencies being considered for the converter. Total power
dissipation in the switch is the sum of switching loss and conduction loss. Switching losses are the combination
of the gate charge loss, C
OSS
loss and turnon and turnoff losses:
P
GATE
+ Q
GATE
V
GATE
f
S
P
COSS
+
1
2
C
OSS
V
2
OFF
f
S
P
ON
) P
OFF
+
1
2
V
OFF
I
L
ǒ
t
ON
) t
OFF
Ǔ
f
S
where Q
GATE
is the total gate charge, V
GATE
is the gate drive voltage, f
S
is the clock frequency, C
OSS
is the drain
source capacitance of the MOSFET, I
L
is the peak inductor current, t
ON
and t
OFF
are the switching times
(estimated using device parameters R
GATE
, Q
GD
and V
TH
) and V
OFF
is the voltage across the switch during the
off time, in this case V
OFF
= V
OUT
.
Conduction loss is calculated as the product of the R
DS(on)
of the switch (at the worst case junction temperature)
and the square of RMS current:
P
COND
+ R
DS(on)
K I
2
RMS
where K is the temperature factor found in the manufacturer’s R
DS(on)
vs. junction temperature curves.
Calculating these losses and plotting against frequency gives a curve that enables the designer to determine
either which manufacturer’s device has the best performance at the desired switching frequency, or which
switching frequency has the least total loss for a particular power switch. For this design example an IRFP450
HEXFET from International Rectifier was chosen because of its low R
DS(on)
and its V
DSS
rating. The IRFP450’s
R
DS(on)
of 0.4 Ω and the maximum V
DSS
of 500 V made it an ideal choice. An excellent review of this procedure
can be found in the Unitrode Power Supply Design Seminar SEM1200, Topic 6, Design Review: 140 W, [Multiple
Output High Density DC/DC Converter].
Softstart
The softstart circuitry is used to prevent overshoot of the output voltage during start up. This is accomplished
by bringing up the voltage amplifier’s output (V
VAOUT
) slowly which allows for the PWM duty cycle to increase
slowly. Please use the following equation to select a capacitor for the softstart pin.
In this example t
DELAY
is equal to 7.5 ms, which
would yield a C
SS
of 10 nF.
C
SS
+
10 mA t
DELAY
7.5 V
In an open-loop test circuit, shorting the softstart pin to ground does not ensure 0% duty cycle. This is due to
the current amplifiers input offset voltage, which could force the current amplifier output high or low depending
on the polarity of the offset voltage. However, in the typical application there is sufficient amount of inrush and
bias current to overcome the current amplifier’s offset voltage.
(4)
(5)
(6)
(7)
(8)