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 



SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009

   

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FEATURES

Controls Boost Preregulator to Near-Unity

Power Factor

D Limits Line Distortion

D World Wide Line Operation

D Over-Voltage Protection

D Accurate Power Limiting

D Average Current Mode Control

D Improved Noise Immunity

D Improved Feed-Forward Line Regulation

D Leading Edge Modulation

D 150-µA Typical Start-Up Current

D Low-Power BiCMOS Operation

D 12-V to 17-V Operation

D Frequency Range of 6 kHz to 220 kHz

DESCRIPTION

The UCC3817A and the UCC3818A family

provides all the functions necessary for active

power factor corrected preregulators. The

controller achieves near unity power factor by

shaping the ac input line current waveform to

correspond to that of the ac input line voltage.

Average current mode control maintains stable,

low distortion sinusoidal line current.

Designed in Texas Instrument’s BiCMOS process,

the UCC3817A/UCC3818A offers new features

such as lower start-up current, lower power

dissipation, overvoltage protection, a shunt UVLO

detect circuitry, a leading-edge modulation

technique to reduce ripple current in the bulk

capacitor and an improved, low-offset (±2 mV)

current amplifier to reduce distortion at light load

conditions.

BLOCK DIAGRAM

UDG-03122

VREF9

DRVOUT

GND

CAI

VCC

OVP/EN

VAOUT

1.9 V

PKLMT

7.5 V

REFERENCE

UVLO

16 V/10 V (UCC3817A)

10.5 V/10 V (UCC3818A)

VCC

OSCILLATOR

PWM

LATCH

−

PWM

CAOUT

−

VOLTAGE

ERROR AMP

8.0 V

11VSENSE

VFF

IAC

MOUT

MIRROR

2:1

−

7.5 V

ENABLE

OVP

MULT

OSC

CLK

CURRENT

AMP

16 V (FOR UCC3817A ONLY)

−

0.33 V

ZERO POWER

−

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (32 pages)

PAGE 1
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 FEATURES D Controls Boost Preregulator to Near-Unity D D D D D D D D D D D D DESCRIPTION The UCC3817A and the UCC3818A family provides all the functions necessary for active power factor corrected preregulators. The controller achieves near unity power factor by shaping the ac input line current waveform to correspond to that of the ac input line voltage.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 DESCRIPTION (CONTINUED) The UCC3817A/18A family of PFC Controllers is directly pin for pin compatible with the UCC3817/18 family of devices. Only the output stage of UCC3817A family has been modified to allow use of a smaller external gate drive resistor values.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)† UCCx81xA UNIT Supply voltage VCC 18 V Supply current ICC 20 mA Gate drive current, continuous 0.2 Gate drive current 1.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C for the UCC3817A and TA = −40°C to 85°C for the UCC2817A, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS VREF +0.48 VREF +0.50 VREF +0.52 V Hysteresis 300 500 600 Enable threshold 1.7 1.9 2.1 Enable hysteresis 0.1 0.2 0.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C for the UCC3817A and TA = −40°C to 85°C for the UCC2817A, TA = TJ, VCC = 12 V, RT = 22 kΩ, CT = 270 pF, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Multiplier Section IMOUT, high line, low power output current, (0°C to 85°C) IAC = 500 µA, VFF = 4.7 V, VAOUT = 1.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 PIN ASSIGNMENTS TERMINAL NAME I/O NO.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 Pin Descriptions (cont.) IAC: This input to the analog multiplier is a current proportional to instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (IIAC) to multiplier output. The recommended maximum IIAC is 500 µA. MOUT: The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT.
PAGE 8
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION The UCC3817A is a BiCMOS average current mode boost controller for high power factor, high efficiency preregulator power supplies. Figure 1 shows the UCC3817A in a 250-W PFC preregulator circuit. Off-line switching power converters normally have an input current that is not sinusoidal.
PAGE 9
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Power Stage LBOOST : The boost inductor value is determined by: L BOOST + ǒVIN(min) (DI D Ǔ fs) (2) where D is the duty cycle, ∆I is the inductor ripple current and fS is the switching frequency. For the example circuit a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.
PAGE 10
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Power switch selection: As in any power supply design, tradeoffs between performance, cost and size have to be made. When selecting a power switch, it can be useful to calculate the total power dissipation in the switch for several different devices at the switching frequencies being considered for the converter.
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SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Multiplier The output of the multiplier of the UCC3817A is a signal representing the desired input line current. It is an input to the current amplifier, which programs the current loop to control the input current to give high power factor operation. As such, the proper functioning of the multiplier is key to the success of the design.
PAGE 12
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total harmonic distortion caused by the 120 Hz rectified line voltage. Refer to Unitrode Power Supply Design Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter was adequate for this design. Assuming that an allocation of 1.
PAGE 13
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Voltage Loop The second major source of harmonic distortion is the ripple on the output capacitor at the second harmonic of the line frequency. This ripple is fed back through the error amplifier and appears as a 3rd harmonic ripple at the input to the multiplier.
PAGE 14
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION In this example Cf equals 150 nF. Resistor Rf sets the dc gain of the error amplifier and thus determines the frequency of the pole of the error amplifier. The location of the pole can be found by setting the gain of the loop equation to one and solving for the crossover frequency.
PAGE 15
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION RI is the RMOUT resistor, previously calculated to be 3.9 kΩ. (refer to Figure 3). The gain of the current amplifier is Rf/RI, so multiplying RI by GEA gives the value of Rf, in this case approximately 12 kΩ. Setting a zero at the crossover frequency and a pole at half the switching frequency completes the current loop compensation.
PAGE 16
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Start Up The UCC3818A version of the device is intended to have VCC connected to a 12-V supply voltage. The UCC3817A has an internal shunt regulator enabling the device to be powered from bootstrap circuitry as shown in the typical application circuit of Figure 1. The current drawn by the UCC3817A during undervoltage lockout, or start-up current, is typically 150 µA.
PAGE 17
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION UDG-97130-1 Figure 5. Simplified Representation of a 2-Stage PFC Power Supply UDG-97131 Figure 6. Timing Waveforms for Synchronization Scheme www.ti.
PAGE 18
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION Table 1 illustrates that the boost capacitor ripple current can be reduced by about 50% at nominal line and about 30% at high line with the synchronization scheme facilitated by the UCC3817A. Figure 7 shows the suggested technique for synchronizing the UCC3817A to the downstream converter. With this technique, maximum ripple reduction as shown in Figure 6 is achievable.
PAGE 19
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION REFERENCE VOLTAGE vs REFERENCE CURRENT REFERENCE VOLTAGE vs SUPPLY VOLTAGE 7.510 VREF − Reference Voltage − V VREF − Reference Voltage − V 7.60 7.55 7.50 7.45 7.505 7.500 7.495 7.490 7.
PAGE 20
SLUS577C − SEPTEMBER, 2003 − REVISED MARCH 2009 APPLICATION INFORMATION MULTIPLIER CONSTANT POWER PERFORMANCE (VFF × IMOUT) − µW 500 400 VAOUT = 5 V 300 VAOUT = 4 V 200 VAOUT = 3 V 100 VAOUT = 2 V 0 0.0 1.0 2.0 3.0 4.0 5.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.3 2.1 8.0 16.0 Q1 UCC2817ADR SOIC D 16 2500 330.0 16.4 6.5 UCC2817APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 UCC2818ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC2817ADR SOIC D 16 2500 333.2 345.9 28.6 UCC2817APWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC2818ADR SOIC D 16 2500 333.2 345.9 28.6 UCC2818APWR TSSOP PW 16 2000 367.0 367.0 35.0 UCC3817ADR SOIC D 16 2500 333.2 345.9 28.6 UCC3818ADR SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.