Datasheet

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DEVICE INFORMATION
UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
COMP1 5 O
Low impedance output of the error amplifiers.
COMP2 12 O
CS1 6 I Current sense inputs to the PWM comparators. These inputs have leading edge blanking. For
most applications, no input filtering is required. Leading edge blanking disconnects the CS inputs
from all internal circuits for the first 55 ns of each PWM cycle. When used with very slow diodes or
CS2 11 I
in other applications where the current sense signal is unusually noisy, a small current-sense R-C
filter may be required.
The timing capacitor of the oscillator. Recommended values of CT are between 100 pF and 1 nF.
CT 2 O
Connect the timing capacitor directly across CT and GND.
A logic input which disables PWM 2 when low. This input has no effect on PWM 1. This input is
internally pulled high. In most applications it can be left floating. In unusually noisy applications,
ENABLE2 14 I
the input should be bypassed with a 1-nF ceramic capacitor. This input has TTL compatible
thresholds.
FB1 4 I
The high impedance inverting inputs of the error amplifiers.
FB2 13 I
To separate noise from the critical control circuits, this part has two different ground connections:
GND 8 – GND and PWRGND. GND and PWRGND must be electrically connected together. However, use
care to avoid coupling noise into GND.
OUT1 7 O The high-current push-pull outputs of the PWM are intended to drive power MOSFET gates
through a small resistor. This resistor acts as both a current limiting resistor and as a damping
OUT2 10 O
impedance to minimize ringing and overshoot.
To separate noise from the critical control circuits, this part has two different ground connections:
PWRGND 9 –
GND and PWRGND. GND and PWRGND must be electrically connected together.
The output of the 5-V reference. Bypass REF to GND with a ceramic capacitor ≥ 0.01-µF for best
REF 15 O
performance.
The oscillator charging current is set by the value of the resistor connected from RT to GND. This
pin is regulated to 1 V, but the actual charging current is 10 V/RT. Recommended values of RT
RT 3 O
are between 10 k Ω and 470 k Ω . For a given frequency, higher timing resistors give higher
maximum duty cycle and slightly lower overall power consumption.
This logic input can be used to synchronize the oscillator to a free running oscillator in another
SYNC 1 I part. This pin is edge triggered with TTL thresholds, and requires at least a 10-ns-wide pulse. If
unused, this pin can be grounded, open circuited, or connected to REF.
The power input to the device. This pin supplies current to all functions including the high current
VCC 16 I output stages and the precision reference. Therefore, it is critical that VCC be directly bypassed to
PWRGND with an 0.1-µF ceramic capacitor.
5
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