Datasheet
SLUU087B
12
10-Watt Flyback Converter Using the UCC3809
where C
OUT
is the total capacitance of the output capacitor bank and ESR is the parallel combination of the
output capacitor’s equivalent series resistance. The power stage contributes a pole located at:
F
PWRstg(pole)
+
2
2 p R
OUT
C
OUT
Note that this pole is load dependent. The control to output gain is calculated by the following equation:
G + K
R
OUT
ǒ
L
SEC
f
SW
Ǔ
2
Ǹ
I
P
+
2 I
SC(sec)
1 * D
MAX
K +
I
P
V
C
where R
OUT
is the load, L
SEC
is the primary inductance reflected to the secondary side, and I
SC(sec)
is the
secondary-side short-circuit current, V
C
is the reference voltage of the TLV431, or 1.24 V.
Once the gain and corner frequencies have been determined, a bode plot can be constructed of the
pre-compensated converter. Sampling theory limits the maximum-crossover frequency to one half the switching
frequency. Practicality limits it even further; the system is unstable if the crossover frequency is more than
f
SW
/2πD
MAX
. For this design, the crossover frequency was set at approximately 1 kHz. The error amplifier
requires 38-dB of gain at this frequency. A pole is also needed to cancel the ESR zero. This pole is added a
decade below the corner frequency of the ESR zero, resulting in an increase in low-frequency gain and adding
45 degrees of phase margin. The error-amplifier compensation is determined using the following equation:
EA
GAIN
+ 20 log
ǒ
R
F
R
I
Ǔ
where R
I
is equal to R21 + R17, referring to Figure 1, the feedback resistor, R
F
, shown as R15 in Figure 1, is
easily determined. The feedback capacitor (shown as C16 on the schematic), which, when combined with the
feedback resistor adds the ESR canceling pole, is calculated using:
C
F
+
1
2 p F
P
R
F
where F
P
is set at one-tenth F
ESR
(zero)
.
The resultant phase margin is approximately 100 degrees.