Datasheet

UDG-- 01114
UCC37321
ENBL
1
2
3
4
IN
7
6
5
8
OUT
OUT
INPUT
VDD
VDD VDD
R
SNS
0.1 Ω
V
SNS
100 μF
AL EL
1 Fμ
CER
C2
1 Fμ
C3
100 μF
4.5 V
D
ADJ
D
SCHOTTKY
AGND
PGND
UCC27321 , UCC27322
UCC37321, UCC37322
SLUS504G –SEPTEMBER 2002–REVISED MAY 2013 www.ti.com
The circuit in Figure 4 is utilized to test the current source capability with the output clamped to around 5 V with a
string of Zener diodes. The UCC37321 is found to source 9 A at V
DD
= 15 V.
Figure 4. Source Current Test Circuit
It should be noted that the current sink capability is slightly stronger than the current source capability at lower
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the
current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.
In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients
which may turn the device back ON.
Operational Circuit Layout
It can be a significant challenge to avoid the overshoot/undershoot and ringing issues that can arise from circuit
layout.The low impedance of these drivers and their high di/dt can induce ringing between parasitic inductances
and capacitances in the circuit. Utmost care must be used in the circuit layout.
In general, position the driver physically as close to its load as possible. Place a 1-µF bypass capacitor as close
to the output side of the driver as possible, connecting it to pins 1 and 8. Connect a single trace between the two
VDD pins (pin 1 and pin 8); connect a single trace between PGND and AGND (pin 5 and pin 4). If a ground
plane is used, it may be connected to AGND; do not extend the plane beneath the output side of the package
(pins 5 – 8). Connect the load to both OUT pins (pins 7 and 6) with a single trace on the adjacent layer to the
component layer; route the return current path for the output on the component side, directly over the output
path.
Extreme conditions may require decoupling the input power and ground connections from the output power and
ground connections. The UCCx7321/2 has a feature that allows the user to take these extreme measures, if
necessary. There is a small amount of internal impedance of about 15 Ω between the AGND and PGND pins;
there is also a small amount of impedance (∼30 Ω) between the two VDD pins. In order to take advantage of this
feature, connect a 1-µF bypass capacitor between VDD and PGND (pins 5 and 8) and connect a 0.1-µF bypass
capacitor between VDD and AGND (pins 1 and 4). Further decoupling can be achieved by connecting between
the two VDD pins with a jumper that passes through a 40-MHz ferrite bead and connect bias power only to pin 8.
Even more decoupling can be achieved by connecting between AGND and PGND with a pair of anti-parallel
diodes (anode connected to cathode and cathode connected to anode).
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Product Folder Links: UCC27321 UCC27322 UCC37321 UCC37322