Datasheet

UCC29910A

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SLUSAK8A – MAY 2011– REVISED JUNE 2011

BULK OV Clamp

The low bandwidth of the normal control loop prevents it from controlling an increase in VBULK due for example,

to a large step reduction in the load on the VBULK output. This clamp activates within 120 µs if the voltage at the

VBULK pin exceeds 107% of V

. When activated, it blanks the gate control logic output and the PFCDRV pin is

held low. This clamp is non-latching so it releases once VBULK falls below trip level, i.e., 107% of VNM. For a

short duration BULK OV clamp event, recovery will be back to the operating mode in place at the beginning of

the event (usually normal mode). If VBULK stays above the clamp level for long enough, the conditions for entry

into light load mode may be satisfied and recovery will be into light load mode.

Reference

All of the measurement functions within the UCC29910A use the REFIN pin for their reference voltage, these

include (V

, V

B(max)

, V

B(min)

and V

). The specifications are written on the assumption that the

reference voltage is 1.500 V and variations in this will proportionally affect the accuracy of measurements. The

REFIN pin should be bypassed to V

to reduce noise. A 100-nF capacitor connected between pin 6 and pin 14

is recommended, this part should be placed as close as possible to the controller and connected with minimum

length tracks.

Fault Latch

This latch is activated by pulling the FAULT pin to V

. When activated the current PWM cycle is terminated,

PFCDRV is held Low and BIASCTRL is set low. The controller enters SmartStart mode if the FAULT input clears

high in less than t

(100 µs). If the FAULT input persists for longer than t

the controller enters a latched shutdown

mode The latched state is cleared if the LINESNS pin is held below 215 mV

RMS

for 120 ms. The controller will

re-start after a 10-s delay, providing LINESNS has recovered to at least V

. Alternatively cycling chip power off

then on will also clear the latched state. Connecting a 1-nF capacitor between the FAULT pin and VSS is

recommended to reduce the risk of nuisance tripping.

PFC Drive

A power MOSFET driver, such as an NPN and PNP transistor or a UCC27324 will normally be required to

convert the PFCDRV output from the UCC29910A to the current and voltage levels typically needed to ensure

correct power MOSFET operation.

Product Folder Link(s): UCC29910A