Datasheet

UCC29910A
SLUSAK8A –MAY 2011– REVISED JUNE 2011 www.ti.com
Control system
The UCC29910A uses an average current mode control loop to regulate the output voltage, this eliminates the
need for slope compensation. The two inputs to this control loop are the voltages at the VBULK and CS (Current
Sense) pins.
Voltage Loop – PI Error Amp
The output of the PI (Proportional Integral) Error Amplifier is proportional to the difference between the voltages
at the VBULK pin and the REFIN pins. The integral term in the amplifier drives the steady state error to zero but,
in common with virtually all PFC controllers the control loop bandwidth is very low – approximately 10 Hz in this
case.
Current Sense
The CS pins allow the UCC29910A to sense the average current in the power stage. The current sense signal is
subtracted from the demand signal from the error amplifier and the result is used to set the PFCDRV duty cycle.
PWM Generator
The PWM Generator generates a duty cycle signal which is fed into the gate control logic. The duty cycle
commanded is proportional to the demand signal from the control loop.
Light Load Detect / Burst Mode Control
As the load on the power stage decreases the standing losses due to, for example, the drive power needed to
effect switching of the main power MOSFET, becomes an increasingly important proportion of the whole. The
UCC29910A includes a SmartBurst light-load mode which significantly reduces these standing losses. In Normal
Mode operation the UCC29910A continuously switches the power MOSFET, in light load the power MOSFET is
switched in a burst mode. Power losses are reduced very significantly between bursts because there is no
switching activity in the power train. During the burst, the power train is efficiently operated at close to full power.
The average power transferred from input to output is controlled by modulating the interval between bursts.
Gate Control Logic
The Gate Control Logic block takes the inputs from a number of sources and outputs the PFCDRV signal.
The fault latch output disables the gate control logic and sets the PFCDRV to low.
The BULK OV clamp forces the PFCDRV output low if the voltage at the VBULK pin exceeds 107% of V
NM
.
The Start-up burst signal determines the PFCDRV on and off times during the start-up phase before the PWM
generator becomes active.
The PFC duty cycle signal sets the PFCDRV output duty cycle demand in normal mode. A line dependent D
MIN
and a 90% D
MAX
limit are applied.
The light load detect burst mode control block controls operation during light load mode and entry to and exit
from this mode.
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