Datasheet

3
14 VSS
4
Oscillator
7
Start-up Burst
CLK
13 PFCDRV
6
9
2
CS
Gate Control
Logic
8
FAULT
“Smart-Start”
Soft Start
Burst Control
1
VDD
12
1.92 V
POR
+
Brown- out
Detection & Filter
Latch reset detect
5
Startup
Bias Control
CS
VBULK
BIASSNS
BIASCTRL
NC
REFIN
Fault Latch
Run/ Stop
EN
EN
Voltage Loop
PI Error Amp
REF
REF
-
+
PWM
Generator
EN
EN
BULK OV
Clamp
Disable
PFCDRV Blanking
PFC Duty Cycle
Light Load Detect
Burst Mode
Control
EN
LINESNS
10
TST
UDG-11105
UCC29910A
11
NC
UCC29910A
SLUSAK8A –MAY 2011– REVISED JUNE 2011 www.ti.com
Pin 8 – FAULT: This pin when pulled low causes PFCDRV and BIASCTRL to go low, typically within 10 us. After
a 100 us delay the FAULT input is sampled again. If the FAULT has cleared high, the UCC29910A goes into
SmartStart mode. If the FAULT input is still low the device enters a latched shutdown state.
Pin 9 – BIASSNS: This pin is used to sense the PFC stage bias rail (normally in the 8 V to 12 V range to drive
the PFC power MOSFET) during start-up to allow control of the external start-up FET. The voltage at this pin
must be greater than V
B(max)
before PFCDRV switching commences. If the voltage drops below V
B(min)
the
BIASCTRL output goes low, which can enable an external start-up FET.
Pin 10 – TST: This pin provides no user function. It must be connected to VDD.
Pin 11 – NC: This pin is for internal use only, and must be normally left open.
Pin 12 – BIASCTRL: This pin allows control of an external start-up FET.
Pin 13 – PFCDRV: This pin is used to drive the low-side PFC FET indirectly. This pin should be connected to a
level-shifting gate driver to provide the required drive signal amplitude for typical high voltage power FETs. For
this drive signal, D
MAX
is limited to 90% duty cycle.
Pin 14 – VSS: This pin is the common ground connection for the device.
UCC29910A Functional Block Diagram
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Product Folder Link(s): UCC29910A