Datasheet

UCC29910A

www.ti.com

SLUSAK8A – MAY 2011– REVISED JUNE 2011

Detailed Pin Description

Pin 1 – VDD: This pin supplies power to the device. A minimum supply voltage level of 3.0 V and maximum of

3.6 V is recommended.

Pin 2 – VBULK: The output voltage level, V

BULK

is sensed on this pin. The HV bulk sensing network should be

scaled so that the desired output voltage produces V

at this pin. The Thevenin impedance at this pin should be

below 20 kΩ, with appropriate capacitance provided for noise filtering.

NOTE

The V

BULK

scaling and LINESNS scaling must maintain a ratio of close to 4:1 to ensure

optimum operation of the SmartStart algorithm.

Pin 3 – CS: This pin senses the current in the PFC stage. Both CS pins must be connected to the current sense

signal and it is not permissible to leave one floating. The CS pins are intended to sense average low side PFC

FET current directly. A 150-mΩ current sense resistor value is optimal for powers of 90 W, with appropriate

scaling for higher power levels. The recommended feed impedance level is approximately 100 Ω, and a capacitor

of 1 µF is also recommended to act as a filter on the input current and to minimise noise pickup. A smaller value

capacitor may result in possible current loop instability. A larger cap value may result in poor Power Factor (PF)

due to excessive current signal phase shift. UCC29910A does not provide cycle-by-cycle inductor current

limiting. An external circuit is needed if this type of protection is required.

Pin 4 – LINESNS: This pin senses the rectified line voltage. The internal reference for this pin is internally scaled

to ¼ of the VBULK reference.

NOTE

The LINESNS scaling and VBULK scaling must maintain a ratio of close to 1:4 to ensure

optimum operation of the SmartStart algorithm.

A peak of high-line voltage (typically 373-V for 264-VAC input) should be scaled to correspond to 1.158 V

this pin. A pin feed impedance of less than 20 kΩ is recommended along with a filter capacitor of at least 2.2 nF

for noise filtering. The RMS voltage at this pin must be greater than VBH before PFCDRV can start switching.

The PFCDRV will go low if the RMS voltage drops below the brownout level V

(21 ms timeout). The controller

will not start if VLINESNS exceeds VLM, (VBULK = 0 V).

Pin 5 – CS: See pin 3 description above. This pin senses the current in the PFC stage, pins 3 and 5 must be

connected together.

Pin 6 – REFIN: This pin must be connected to an external accurate 1.500 V reference source, e.g. using a

suitable shunt regulator with voltage setting resistors such as TLVH431A. The reference voltage must be

established within 100 ms after VDD reaches 3.0 V.

Pin 7 – NC: This pin is not used, and should be left open.

Product Folder Link(s): UCC29910A