Datasheet

UCC29910A
SLUSAK8A –MAY 2011– REVISED JUNE 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PART NUMBER PACKAGE PACKING
UCC29910APW Plastic, 14-Pin TSSOP (PW) 90-Pc. Tube
UCC29910APWR Plastic, 14-Pin TSSOP (PW) 2000-Pc. Tape and Reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)(2)(3)
VALUE UNIT
4.1
V
DD
Supply Voltage
-0.3 V
Voltage: All pins −0.3 to VDD + 0.3
T
A
Operating free air temperature,
(4)
−40 to 105
T
J
Operational junction temperature,
(4)
°C
T
STG
Storage temperature
(4)
−40 to 105
Lead temperature (10 seconds) 260
(1) These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at
these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability.
(2) All voltages are with respect to VSS.
(3) All currents are positive into the terminal, negative out of the terminal.
(4) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
THERMAL INFORMATION
THERMAL METRIC
(1)
UNITS
PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
θ
JB
Junction-to-board thermal resistance
(4)
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
ψ
JB
Junction-to-board characterization parameter
(6)
θ
JCbot
Junction-to-case (bottom) thermal resistance
(7)
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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