Datasheet
UCC29910A
www.ti.com
SLUSAK8A – MAY 2011– REVISED JUNE 2011
Normal Mode Operation
In normal mode, the VBULK pin is controlled at V
NM
. Due to the slow voltage loop, and low gain at 100/120 Hz,
the voltage loop PI error amp output will be essentially a fixed demand. If the power stage stays in Discontinuous
Conduction Mode (DCM) throughout the half-cycle, then peak current will be proportional to (VHV-V
BULK
) over the
half cycle and I
AVG
is approximately proportional to I
PEAK
. If the power stage transitions into Continuous
Conduction Mode (CCM) during the line cycle, the current loop, responding to the average current, keeps the
peak current flatter, so the line current doesn’t quite follow (V
IN
-V
O
) anymore but average line current is approx
proportional to (VHV-V
BULK
) over the half-cycle. The overall effect is shown in the current waveforms in Figure 3
and Figure 4.
The line voltage is used by the control loop to set dynamic D
MIN
and D
MAX
values.
Transient Response and V
BULK
Regulation
When the UCC29910A is regulating in normal mode, the VBULK pin will be at V
NM
. An AC ripple at twice line
frequency will be superimposed on this as the PFC stage drives current into the bulk capacitors. The amplitude
of this ripple will be a function of line frequency, capacitance value and load current. Due to the necessary low
control loop bandwidth V
BULK
will reduce in response to a step load increase. If the load step is large enough to
cause the V
BULK
pin to reduce to less than 0.992 V the loop response is temporarily speeded up until this voltage
has been increased back up to 1.043 V at which point the original loop response is restored.
SmartBurst Mode (light load)
As load current reduces the UCC29910A will continue to regulate the voltage at the VBULK pin at V
NM
. It will do
this by reducing the PWMDRV waveform duty cycle, except that any pulses which are commanded to be less
than D
MIN
will be masked and not delivered to the PWMDRV output. The proportion of cycles thus dropped is
counted over a 10-ms window and if it exceeds 10% the UCC29910A changes its operating mode to SmartBurst
mode.
In SmartBurst mode the UCC29910A enters a low power consumption mode to minimize wasted power and
improve light-load efficiency. Every 1 ms (approximately) it samples the voltages at the LINESNS and VBULK
pins. If the voltage at VBULK is still within a target window of 1.087 V to 1.074 V no action is taken. The applied
load will eventually cause the bus voltage to drop below this window and a burst of pulses are then output at the
PFCDRV pin. These drive the PFC FET and thereby recharge the PFC bus capacitance. The most efficient
transfer of power is achieved by minimizing the number of switching events, thus minimizing switching and gate
drive losses. The line voltage sample is used to set the maximum safe duty cycle for the PFCDRV pulses while
keeping the inductor current discontinuous, based on an inductor rating of 600 Vµs. The pulse duty cycle is
ramped from D
MIN
to this maximum value. At the end of the burst, the pulse duty cycle is ramped back to D
MIN
.
Ramping the duty cycle in this manner avoids the sudden application of high power pulses to the power train
which may cause excessive EMI and unwanted audio noise generation. A full SmartBurst pulse will last for 2
ms – including the ramp-up time but excluding the ramp-down time.
The SmartBurst pulse train is terminated if the voltage at the VBULK pin reaches the peak value of the allowed
window, 1.087 V or if it exceeds 2 ms in length. There is a 5-ms minimum time between the start of successive
SmartBurst pulse trains.
The max burst length and minimum burst repetition interval ensure that as load is increased, at some point the
burst rate will become insufficient to maintain V
BULK
. Once the voltage falls below the normal mode setpoint V
NM
at the VBULK pin the controller reverts to normal regulation mode.
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