Datasheet
SLUS431A – MAY 2000 – REVISED DECEMBER 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DETAILED DESCRIPTION
soft start
The soft-start section contains all the circuitry required to produce a user programmable slowly increasing PWM
duty cycle, starting from 0% to a maximum of 72%. The soft-start cycle is triggered either by the initial
primary-side startup procedure or after any one of three user-programmable fault conditions and one fixed-fault
condition. The PWM duty cycle increases according to the charge rate of an user selectable external soft-start
capacitor, connected from the SS pin to GND. The SS capacitor is charged by a nominal 7-µA internal current
source.
Voltage comparators referenced to a 4.0-V threshold monitor the OVS pin, SD pin and the UVS pin and trigger
a soft-start cycle when a fault condition is detected on any of these pins. Should the CS pin rise in voltage above
1.375 V a soft-star cycle is also triggered. The soft-start cycle disables the output driver OUT and holds it in the
low state until the capacitor connected from the SS pin to GND is discharged below 1.0 V by an internal 5-µA
current sink. After this discharge period the PMW output OUT is enabled and the duty cycle is allowed to slowly
increase as before.
synchronization
The SS pin and the FB pin accept the secondary side of a small-signal synchronization transformer. A
series-blocking capacitor inserted in the primary-side of the synchronization transformer is intended to
differentiate the square-wave gate drive output of the secondary-side PWM controller while preventing the
transformer from saturation. The SS capacitor also provides an ac GND at the SS pin or the synchronization
transformer secondary. The small signal synchronization transformer provides galvanic isolation between
primary and secondary side and must have adequate voltage breakdown rating between the primary and
secondary windings.
Two comparators, with an approximate 1.0-V offset each, are connected to the FB pin to provide plus and minus
differential voltage comparison with a 2.0-V deadband between the FB and SS pins. The 2.0-V deadband
prevents inductive backswing of the small signal transformer from giving false secondary-side pulse-edge
detection.
Enough energy must be coupled into the comparator differential inputs to ensure reliable comparator switching.
This requires sufficient voltage overdrive above the 1.0-V comparator threshold and a specified transformer
circuit time constant to provide a minimum synchronization pulse width.
On receiving the first recognizable negative going voltage pulse (turnoff command) generated from the falling
edge of the differentiated square-wave gate drive signal on the secondary-side, the PWM latch is reset and a
synchronization latch is set. After this event all primary-side PMW driver output is slaved to the secondary-side
driver output in both frequency and duty cycle. The triggering of a soft-start cycle by a fault condition resets the
synchronization latch to again allow the internal startup oscillator to control the PWM latch.
pulse-width modulation
The PWM section consists of a reset dominant SR latch with necessary logical gating on the SET input to allow
control from the free running startup oscillator until feedback from the secondary-side PWM gate drive output
is detected. After the occurrence of detectable feedback from the secondary-side gate driver, the control of the
primary-side PWM latch is handed off to the secondary-side PWM controller. A nine-input OR gate on the PWM
latch reset dominant input allows the numerous fault conditions to reset the PWM latch and control from either
the startup oscillator or feedback from the secondary-side PWM output driver.