Datasheet
SLUS431A – MAY 2000 – REVISED DECEMBER 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing resistor (RT)
A resistor from this pin to AGND establishes a current,
I
SET
2V
RT
that is mirrored internally for several functions. It establishes the free-running startup switching frequency with
an internal capacitor according to the relationship,
fs
8.0 10
9
RT
The startup oscillator has a rise and fall time set to limit the duty-cycle of the power switch to a maximum of 72%,
a limit that is maintained even after the feedback signal takes command. The range of RT is 22.2 kΩ to 133 kΩ,
giving a free-run frequency range range of 60 kHz to 360 kHz, respectively. Variations in the free-running
oscillator frequency overtemperature are very small. The typical temperature coefficient is –40 Hz per degree
Celsius, measured at 150 kHz.
shutdown (SD)
This pin is the input to the shutdown circuit. Like OVS, this pin also sets the shutdown latch when a threshold
above 4 V is exceeded. The primary intent of this input is to allow the use of an external capacitor to program
a delay between the onset of current limiting and the issuance of a shutdown command by integrating current
pulses that appear on this pin with each activation of the CS input. This pin is pulled low with a current sink of
0.33/RT when there is no CS signal. The shutdown function can be disabled by connecting SD pin to AGND.
soft-start (SS)
The pin implements the primary-side soft-start function. This is the connection point for an external capacitor
that determines the rate of increase in commanded pulse width for the power switch at startup. It also serves
as the ac ground return for the feedback pulse transformer to provide a tracking bias for the FB input.
start bias regulator (START)
In conjunction with an external depletion-mode N-channel FET, such as the Supertex DN2530, this pin can be
used to develop a regulated voltage of 12 V at VDD and thereby minimize or eliminate continuous current drain
when starting from a variable high voltage source. If this function is unused, this pin can be left open.
power (VDD)
This is the power input connection for all the control circuitry and, in addition, conducts all the gate charge current
for the power FET. It should be closely bypassed with at least 1.0-µF to PGND and 1.0-µF to AGND. This pin
is internally shunt regulated to clamp at 17.5V to protect the internal components so if a voltage source above
this value is possible, external current limiting must be provided.
volt-second clamp (VS)
This pin provides a volt–second clamp for the operation of the transformer–driving power switch with the aid
of an external capacitor to ground and a high value resistor to the transformer’s voltage source (Vin). With the
initiation of each power pulse, the circuit releases an internal grounding clamp across the capacitor allowing
it to charge with a current from the resistor proportional to the input voltage. If this pin reaches 4 V prior to output
termination from other control functions, then this ends the power pulse.
T
VS
1.61 R
VS
C
VS
R
VS
100