Datasheet
SLUS431A – MAY 2000 – REVISED DECEMBER 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics V
DD
= 12 V, RT = 53.3 kΩ, C
VDD
= 1 µF, C
REF
= 0.1 µF, C
SS
= 0.01 µF,
R
OUT
= 4 Ω, C
OUT
= 1 nF and T
A
= T
J
(unless otherwise stated) (continued)
current sense section (CS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Threshold
Pulse-by-pulse 0.9 1 1.1 V
Threshold
Immediate 1.3 1.4 1.5 V
Input bias CS = 1.1 V pulsed 0.2 µA
Delay time CS to OUT 60 100 140 ns
On resistance 600 800 1000 Ω
oscillator section
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Frequency 135 150 165 kHz
Frequency change with voltage V
DD
= 10 V to 12 V 0.02 0.2 %/V
Minimum duty cycle 0%
Maximum duty cycle 69% 72% 75%
volt-second section (VS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Threshold 3.68 4 4.32 V
Input bias 0.2 µA
On resistance 600 800 1000 Ω
output section (OUT)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Low-level output voltage I
OUT
= 100 mA (dc) See Note 1 0.7 1.0 V
High-level output voltage I
OUT
= –40 mA (dc) See Note 2 0.56 1.0 V
Low-level output voltage during UVLO I
OUT
= 20 mA (dc), V
DD
= 7.5 V 1.5 V
Rise time 30 60 ns
Fall time 15 30 ns
bias regulator section (START)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Bias regulator V
DD
– START = 0.5 V 11.7 12.1 12.5 V
Override voltage V
DD
– START = 1.0 V, See Note 3 12.2 V
feedback section (FB)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
input bias current FB = 4.5 V, SS = 0 V 0.4 µA
Negative compliance voltage IFB = –100 mA, SS = 0 V –6.8 –7.2 –7.6 V
Delay time, FB–SS to OUT, rising edge FB–SS Pulsed = 2 V, FB = SS 40 70 100 ns
Delay time, FB–SS to OUT, falling edge FB–SS Pulsed = 2 V, FB = SS 50 85 120 ns
NOTES: 1. OUT Low, nominal of 0.7 V reflects the 3 Ω DMOS ON resistance plus 4 Ω R
SERIES
.
2. OUT High (VDD–OUT), nominal of 0.56 V reflects the 10 Ω HVPMOS ON resistance plus 4 Ω R
SERIES
.
3. The override V
DD
voltage for shutting off the bias regulation is 100 mV higher than the bias regulator voltage.