Datasheet
SLUS431A – MAY 2000 – REVISED DECEMBER 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DETAILED DESCRIPTION
start regulator and VDD clamp
To facilitate the primary-side startup, a V
DD
= 12V voltage regulator may be implemented by using an external
depletion-mode FET. The gate of this device is then connected to the START pin, the source terminal is attached
to the VDD pin, and the drain is tied to the HV primary-side power input that is derived from the rectified line
voltage. An auxiliary bootstrap winding off the main power transformer can be used to generate a bias voltage
greater than 12 V, that effectively shuts down the 12-V regulator and increase the efficiency of the biasing
solution during normal operation.
To ensure that the absolute-maximum voltage ratings of internal devices are not violated, an internal-shunt
voltage regulator is provided to clamp the VDD pin at a nominal 17.5-V maximum voltage. Similarly to other
shunt or Zener-like voltage regulator circuits, the current through the internal VDD clamp must be limited below
the maximum current level indicated in the datasheet. In addition to limiting the current through the clamp circuit,
the maximum power dissipation capability of the particular package used in the application must be considered.
OUT driver
An internal output driver (OUT) is provided to drive the gate of an external N–channel power MOSFET. The
output driver consists of a nominal 4.0-W ON-resistance P-channel MOSFET for turn-on, and a nominal 2.0-Ω
ON resistance DMOS FET utilized during the turn–off of the external MOSFET transistor. An external series gate
resistance is specified to maintain an acceptable safe operating area (SOA) for the DMOS device of the internal
output driver. As discussed in the UVLO section of this datasheet, the undervoltage lockout (UVLO) circuit holds
the PWM gate driver output low while UVLO conditions exists.