Datasheet
SLUS431A – MAY 2000 – REVISED DECEMBER 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DETAILED DESCRIPTION
undervoltage lockout
The undervoltage lockout (UVLO) circuit enables normal operation after VDD exceeds the 10.0-V turnon
threshold and permits operation until VDD falls below the 8-V turnoff threshold. While activated, the UVLO circuit
holds the PWM gate driver output (OUT) and the internal-reference buffer amplifier output REF low. To ensure
proper soft-start and to prevent false SD detection, internal N-channel MOSFET switches discharge external
capacitors connected to the SS and SD pins during undervoltage conditions.
voltage reference
The 5-V internal reference is connected to the REF pin and must be bypassed using a good quality,
high-frequency capacitor. This 5-V reference is not available externally while the chip is disabled by the
undervoltage lockout circuit.
current sensing
The current sense (CS) circuit monitors the voltage across a ground referenced current sense resistor,
connected between the source of the external power MOSFET and GND. The signal amplitude at the CS pin
is compared to two thresholds (1.0 V, and 1.375 V respectively) by two independent voltage comparators.
A voltage level greater than 1.0 V, but less than 1.375 V, sets the reset dominant shutdown latch and resets
the PWM latch. The SD latch is reset by the startup oscillator arriving at its 4.0 V compare threshold. When the
SD latch is set, a scaled current, I
SD
= –(1/6) × (I
RT
), charges an user-selected external capacitor connected
between the SD pin and GND. When the SD latch is reset, a scaled current I
SD
= (1/10)*(1/6) ×(IRT), discharges
the user-selected capacitor connected between the SD pin and GND.
A current-sense voltage greater than 1.375 V immediately triggers a SD event and also reset the PWM latch.
During the off period of the PWM latch, any capacitance connected to the CS pin is discharged to GND potential
by an internal 800-Ω device.
volt-second clamp
The volt-second (VS) clamp circuit monitors the voltage at the VS pin produced by an external-series RC circuit.
The resistor is connected from the HV primary-side power input, that is derived from the rectified line voltage,
to the VS pin. The capacitor is from the VS pin to GND and being charged by the resistor during the on-time
of the OUT driver. The resulting exponential voltage at the VS pin is monitored by a voltage comparator with
a 4.0-V threshold. Should the voltage at the VS pin exceed 4.0-V, the PWM latch is reset, and as a result the
output drive signal is terminated. This RC circuit can be tailored to prevent the power transformer from saturation
by effectively limiting the applied maximum volt-second product across the primary winding. During the off
period of the PWM output driver the VS capacitor is discharged to GND potential by an internal switch with 800Ω
on resistance.