Datasheet
SLUS430A – APRIL 1999 – REVISED DECEMBER 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DETAILED DESCRIPTION
UVLO and REF
The under voltage lockout (UVLO) circuit enables normal operation after VDD exceeds the 10.0-V turnon
threshold and permits operation until VDD falls below the 8-V turnoff threshold. While activated, the UVLO circuit
holds the PWM gate driver output (OUT) and the internal-reference buffer amplifier output REF low. To insure
proper soft-start, internal N-channel MOSFET switches discharge external capacitor connected to the SS pin
during undervoltage conditions.
The 5-V internal reference is connected to the REF pin and must be bypassed using a good quality,
high-frequency capacitor. This 5-V reference is not available externally while the chip is disabled by the under
voltage lockout circuit.
current sense
The current sense (CS) circuit monitors the voltage across a ground referenced current sense resistor,
connected between the source of the external power MOSFET and GND. The signal amplitude at the CS pin
is compared to two thresholds, (1.0 V and 1.375 V respectively), by two independent voltage comparators.
A voltage level greater than 1.0 V, but less than 1.375 V, sets the reset dominant shutdown latch and resets the
PWM latch. The SD latch is reset when the startup oscillator arrives at its 4.0-V threshold.
During the OFF period of the PWM latch, any capacitance connected to the CS pin is discharged to GND
potential by an internal 800-Ω device.
VDD clamp
To insure that the absolute maximum voltage ratings of internal devices are not violated, an internal shunt
voltage regulator is provided to clamp the VDD pin at a nominal 17.5-V maximum voltage. Similarly to other
shunt or Zener-like voltage regulator circuits, the current through the internal VDD clamp must be limited below
the maximum current level indicated in the datasheet. In addition to limiting the current through the clamp circuit,
the maximum power dissipation capability of the particular package used in the application has to be
considered.
OUT driver
An internal output driver (OUT) is provided to drive the gate of an external N–channel power MOSFET. The
output driver consists of a nominal 4.0-Ω ON-resistance P-channel MOSFET for turnon, and a nominal 2.0-Ω
ON-resistance D–channel MOSFET used during the turn–off of the external MOSFET transistor. An external
series gate resistance is specified to maintain an acceptable SOA (Safe Operating Area) for the DMOS device
of the internal output driver. As discussed in the UVLO section before, the under voltage lockout (UVLO) circuit
holds the PWM gate driver output low while UVLO conditions exists.