Datasheet

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  
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SLUS430A – APRIL 1999 – REVISED DECEMBER 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics V
DD
= 12 V, RT = 53.3 kΩ, C
VDD
= 1 µF, C
REF
= 0.1 mF, C
SS
= 0.01 µF,
R
OUT
= 4 Ω, C
OUT
= 1 nF and T
A
= T
J
(unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Supply Section (VDD)
Clamp voltage I
VDD
= 10mA 16 17.5 19 V
Operating current No load, C
OUT
= 0 1.8 2.3 2.8 mA
Starting current V
DD
= 9V 100 150 200 µA
Undervoltage Lockout Section
Start threshold voltage 9.5 10 10.5 V
Hysteresis voltage 1.7 2 2.3 V
Voltage Reference Section (REF)
Reference voltage 4.75 5.0 5.25 V
Load regulation voltage I
REF
= 0 mA to –2.5 mA 3 5 mV
Line regulation voltage V
DD
= 10 V to 12 V 3 5 mV
Short-circuit current 8 10 16 mA
Soft-Start Section (SS)
Discharge current SD = 4.5 V Pulsed 3 5 7 µA
Charge current SD = 4.5 V Pulsed –5 –7 –10 µA
Low–threshold voltage 0.9 1 1.1 V
Clamp threshold voltage 4.5 5 5.5 V
ON resistance V
DD
= 7.5 V 2.5 3.3 5 kΩ
Current Sense Section (CS)
Threshold voltage
Pulse–by–pulse 0.9 1 1.1 V
Threshold voltage
Immediate 1.3 1.4 1.5 V
Input bias current CS = 1.1 V pulsed 0.2 µA
Delay time CS to OUT 60 100 140 ns
ON resistance 600 800 1000 Ω
Oscillator Section
Frequency 135 150 165 kHz
Frequency change with voltage VDD = 10 V to 12 V 0.02 0.2 %/V
Minimum duty cycle 0%
Maximum duty cycle 69% 72% 75%
Output Section (OUT)
Low-level output voltage I
OUT
= 100 mA (dc), See Note 1 0.7 1.0 V
High-level output voltage I
OUT
= –40 mA (dc) , See Note 2 0.56 1.0 V
Low-level output voltage during UVLO I
OUT
= 20 mA (dc), V
DD
= 7.5V 1.5 V
Rise time 30 60 ns
Fall time 15 30 ns
NOTES: 1. OUT low, nominal of 0.7 V reflects the 3-Ω DMOS ON resistance plus 4-Ω R
SERIES
.
2. OUT high (VDD – OUT) nominal of 0.56 V reflects the 10-W HVPMOS ON resistance plus 4-Ω R
SERIES