Datasheet

Programming the Watchdog Period
0V
VDD
t1
0V
VDD
VDD
0V
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14
RESET
WDI
WDO
T
RP
T
WP
t1: Microprocessor is reset.
t2: WDI is toggled some time after reset, but before T expires.
t3: WDI is toggled before expires.
t4: WDI is toggled before expires.
t5: WDI is not toggled before expires and asserts low, triggering the microprocessor to enter an error recovery routine.
t6: The microprocessor’s error recovery routine is executed and WDI is toggled, reinitiating the watchdog timer.
t7: WDI is toggled before expires.
t8: WDI is toggled before expires.
t9: is momentarily triggered, is asserted low for
t10: Microprocessor is reset, pulls high.
t11: WDI is toggled some time after reset, but before expires.
t12: WDI is toggled before expires.
WP
WDO
RES
T
T
T
T
T
T
T
T
WP
WP
WP
WP
WP
RP
WP
WP
RES RES
UCC2946-Q1
www.ti.com ................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009
The watchdog period is programmed with C
WP
as shown in Equation 3 :
T
WP
= 25 × C
WP
(3)
Where
T
WP
is in milliseconds
C
WP
is in nanofarads
A high-quality, low-leakage capacitor should be used for C
WP
. The watchdog input WDI must be toggled with a
high-to-low or low-to-high transition within the watchdog period to prevent WDO from assuming a logic level low.
WDO maintains the low logic level until WDI is toggled or RES is asserted. If at any time RES is asserted, WDO
assumes a high logic state and the watchdog period be reinitiated. Figure 4 shows the timings associated with
the watchdog circuit.
Figure 4. Watchdog Circuit Timing
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