Datasheet

RES
V
Monitored
by RT
DD
Programmed
Threshold
t1: VDD > 1 V, is ensured low.
t2: VDD > programmed threshold, remains low for T .
t3: T expires, pulls high.
t4: Voltage glitch occurs, but is filtered at the RTH pin, remains high.
t5: Voltage glitch occurs whose magnitude and duration is greater than the RTH filter, is asserted for T .
t6: On completion of the T pulse the RTH voltage has returned and is pulled high.
t7: VDD dips below threshold (minus hysteresis), is asserted.
RES
RES
RES
RES
RES
RES
RP
RP
RP
RP
RES
5 V
0 V
5 V
2.5 V
1 V
0 V
t1 t2
t3
t4
t5
t6
t7
T
RP
T
RP
UCC2946-Q1
SGLS273B – OCTOBER 2004 – REVISED MARCH 2009 ................................................................................................................................................. www.ti.com
Figure 3. Reset Circuit Timings
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