Datasheet
Programming the Reset Voltage and Reset Period
V
RESET
+ 1.235
ǒ
R1 ) R2
R2
Ǔ
(1)
UDG−98002
6
7
WDI
WP
8
VDD
3
5
POWER TO
CIRCUITRY
WDO
GND
EDGE DETECT
WATCHDOG
TIMING
100 mV
2
RTH
4
RP
400 nA
POWER
ON RESET
VDD
RESET
NMI
I/O
uP
RES
+
−
+
−
+
−
+
−
+
S Q
QR
1.235 V
SQ
Q R
R2
R1
400 nA
+
+
1.235 V
A3
A2
A1
A0
CLK
CLR
8−BIT
COUNTER
S Q
QR
1
C
RP
C
WP
UCC2946-Q1
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................................................................................................................................................. SGLS273B – OCTOBER 2004 – REVISED MARCH 2009
The UCC2946 allows the reset trip voltage to be programmed with two external resistors. In most applications,
VDD is monitored by the reset circuit, however, the design allows voltages other than VDD to be monitored.
Referring to Figure 2 , the voltage below which reset is asserted is determined by Equation 1 :
To keep quiescent currents low, resistor values in the M Ω range can be used for R1 and R2. A manual reset can
be easily implemented by connecting a momentary push switch in parallel with R2. RES is ensured to be low
with VDD voltages as low as 1 V.
Figure 2. Typical Application Diagram
Once VDD rises above the programmed threshold, RES remains low for the reset period defined by Equation 2 :
T
RP
= 3.125 × C
RP
(2)
Where
T
RP
is time in milliseconds
C
RP
is capacitance in nanofarads
C
RP
is charged with a precision current source of 400 nA, a high-quality, low-leakage capacitor (such as an NPO
ceramic) should be used to maintain timing tolerances. Figure 3 shows the voltage levels and timings associated
with the reset circuit.
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