Datasheet

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SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007
7
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APPLICATION INFORMATION
PROGRAMMING THE WATCHDOG PERIOD
The watchdog period is programmed with C
WP
as follows:
T
WP
+ 25 C
WP
where T
WP
is in milliseconds and C
WP
is in nanofarads. A high-quality, low-leakage capacitor should be used
for C
WP
. The watchdog input WDI must be toggled with a high-to-low or low-to-high transition within the
watchdog period to prevent WDO
from assuming a logic level low. WDO maintains the low logic level until WDI
is toggled or RES
is asserted. If at any time RES is asserted, WDO assumes a high logic state and the watchdog
period be reinitiated. Figure 4 illustrates the timings associated with the watchdog circuit.
0V
VDD
t1
0V
VDD
VDD
0V
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14
RESET
WDI
WDO
T
RP
T
WP
UDG−98007
t1: Microprocessor is reset.
t2: WDI is toggled some time after reset, but before TWP expires.
t3: WDI is toggled before T
WP
expires.
t4: WDI is toggled before T
WP
expires.
t5: WDI is not toggled before TWP expires and WDO
asserts low, triggering the microprocessor to enter an error recovery routine.
t6: The microprocessor’s error recovery routine is executed and WDI is toggled, reinitiating the watchdog timer.
t7: WDI is toggled before T
WP
expires.
t8: WDI is toggled before T
WP
expires.
t9: RES
is momentarily triggered, RES is asserted low for TRP.
t10: Microprocessor is reset, RES
pulls high.
t11: WDI is toggled some time after reset, but before T
WP
expires.
t12: WDI is toggled before T
WP
expires.
t13: WDI is toggled before T
WP
expires.
t14: VDD dips below the reset threshold, RES
is asserted.
Figure 4. Watchdog Circuit Timings
(3)