Datasheet
SLUS198C – FEBUARY 2000 - REVISED - JUNE 2001
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
protecting the UCC3915 from voltage transients
The parasitic inductance associated with the power distribution can cause a voltage spike at V
IN
if the load
current is suddenly interrupted by the UCC3915. It is important to limit the peak of this spike to less than 15 V
to prevent damage to the UCC3915. This voltage spike can be minimized by:
D Reducing the power distribution inductance (e.g., twist the positive (+) and negative (–) leads of the power
supply feeding V
IN
, locate the power supply close to the UCC3915 or use PCB power and ground planes).
D Decoupling V
IN
with a capacitor, C
IN
(refer to Figure 1), located close to the V
IN
pins. This capacitor is
typically 1 µF or less to limit the inrush current.
D Clamping the voltage at V
IN
below 15 V with a Zener diode, D1(refer to Figure 1), located close to the V
IN
pins.
Figure 2. Load Current, Timing-Capacitor Voltage, and Output Voltage of the UCC3915
Under Fault Conditions
estimating maximum load capacitance
For hot-swap applications, the rate at which the total output capacitance can be charged depends on the
maximum-output current available and the nature of the load. For a constant-current, current-limited
application, the output will come up if the load asks for less than the maximum available short-circuit current.
To ensure recovery of a duty cycle from a short-circuited load condition, there is a maximum total output
capacitance which can be charged for a given unit on time (fault time). The design value of on or fault time can
be adjusted by changing the timing capacitor C
T
.