Datasheet

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SLUS274A – JANUARY 1999 – REVISED APRIL 2003
6
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APPLICATION INFORMATION
Typical Fault Mode
Figure 1 shows the detailed circuitry for the fault timing function of the UCCx913. This initial discussion of the
typical fault mode ignores the overload comparator, and current source I3. Once the voltage across the current
sense resistor, R
S
, exceeds 50 mV, a fault has occurred. This causes the timing capacitor to charge with a
combination of 36 µA plus the current from the power limiting amplifier. The PL amplifier is designed to source
current into the CT pin only and to begin sourcing current once the voltage across the output FET exceeds 5 V.
The current I
PL
is related to the voltage across the FET with the following expression:
I
PL
+
V
FET
* 5V
R
PL
where V
FET
is the voltage across the N-channel MOSFET pass device.
(How this feature limits average power dissipation in the pass device is described in further detail in the following
sections). Note that under a condition where the output current is more than the fault level, but less than the
maximum level, V
OUT
≈ V
SS
(input voltage), I
PL
= 0, the C
T
charging current is 36 µA.
UDG–99004
8
5
6
4
OVERCURRENT
COMPARATOR
PL
+
–
SENSE
VSS
VSS
INPUT VOLTAGE
OUTPUT
LOAD
I1
+
–
+
SQ
QR
H=CLOSE
I2
I3
1mA
+
–
+
SENSE
IMAX
+
–
+
–
H=CLOSE
0.5 V
2.5 V
C
T
VSS
TO OUTPUT
DRIVE
H=OFF
OVERLOAD COMPARATOR
CT
FAULT TIMING CIRCUITRY
0.2 V
50 mV
V
DD
R
PL
R
S
5.0 V
1 µA
36 µA
Figure 1. Fault Timing Circuitry Including Power Limit and Overload Comparator
(5)