Datasheet

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COMP
FB
CS
RT/CT
VREF
VDD
OUT
GND
PDIP (P) or SOIC (D) PACKAGE
(TOP VIEW)
Pin Assignments
UCC28C4x-EP
BiCMOS LOW-POWER CURRENT-MODE PWM CONTROLLERS
SGLS352B – DECEMBER 2006 – REVISED MAY 2007
Electrical Characteristics (continued)
V
DD
= 15 V , R
T
= 10 k Ω , C
T
= 3.3 nF, C
VDD
= 0.1 µ F and no load on the outputs, T
A
= T
J
= –55 ° C to 125 ° C for the UCC28C4x
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rise tIme T
A
= 25 ° C, C
LOAD
= 1 nF 25 50 ns
Fall time T
A
= 25 ° C, C
LOAD
= 1 nF 20 40 ns
Undervoltage Lockout (UVLO)
UCC28C42-EP, UCC28C44-EP 13.5 14.5 15.5
Start threshold UCC28C43-EP, UCC28C45-EP 7.8 8.4 9 V
UCC28C40-EP, UCC28C41-EP 6.5 7 7.5
UCC28C42-EP, UCC28C44-EP 8 9 10
Minimum operating voltage UCC28C43-EP, UCC28C45-EP 7 7.6 8.2 V
UCC28C40-EP, UCC28C41-EP 6.1 6.6 7.1
PWM
UCC28C42-EP, UCC28C43-EP, 94 96
Maximum duty cycle UCC28C40-EP, UCC28C44-EP, %
47 48
UCC28C45-EP, UCC28C41-EP
Minimum duty cycle 0%
Current Supply
I
START-UP
Start-up current V
DD
= UVLO start threshold (–0.5 V) 50 100 µ A
I
DD
Operating supply current V
FB
= V
CS
= 0 V 2.3 3 mA
COMP: This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is
frequently used as a control port by utilizing a secondary-side error amplifier to send an error signal across the
secondary-primary isolation boundary through an opto-isolator.
CS: The current-sense pin is the noninverting input to the PWM comparator. This is compared to a signal
proportional to the error amplifier output voltage. A voltage ramp can be applied to this pin to run the device with
a voltage mode control configuration.
FB: This pin is the inverting input to the error amplifier. The noninverting input to the error amplifier is internally
trimmed to 2.5 V ± 1%.
GND: Ground return pin for the output driver stage and the logic-level controller section.
OUT: The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the
UCC28C40, UCC28C42, and UCC28C43 is the same frequency as the oscillator, and can operate near 100%
duty cycle. In the UCC28C41, UCC28C44, and the UCC28C45, the frequency of OUT is one-half that of the
oscillator due to an internal T flipflop. This limits the maximum duty cycle to <50%.
RT/CT: Timing resistor and timing capacitor. The timing capacitor should be connected to the device ground
using minimal trace length.
VDD: Power supply pin for the device. This pin should be bypassed with a 0.1 µ F capacitor with minimal trace
lengths. Additional capacitance may be needed to provide hold up power to the device during startup.
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