Datasheet

UCC28C40, UCC28C41, UCC28C42, UCC28C43, UCC28C44, UCC28C45
UCC38C40, UCC38C41, UCC38C42, UCC38C43, UCC38C44, UCC38C45
SLUS458E -- AUGUST 2001 -- REVISED OCTOBER 2010
3
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electrical characteristics V
DD
= 15 V (See Note 1), R
T
=10kΩ,C
T
=3.3nF,C
VDD
=0.1μF and no load
on the outputs, T
A
=--40°C to 105°C for the UCC28C4x and T
A
=0°Cto70°C for the UCC38C4x,
T
A
=T
J
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Reference Section
Output voltage, initial accuracy T
A
=25°CI
OUT
=1mA 4.9 5.0 5.1 V
Line regulation V
DD
=12Vto18V 0.2 20 mV
Load regulation 1mA to 20mA 3 25 mV
Temperature stability SeeNote2 0.2 0.4 mV/°C
Total output variation SeeNote2 4.82 5.18 V
Output noise voltage 10 Hz to 10 kHz, T
A
=25°C, SeeNote2 50 μV
Long term stability 1000 hours, T
A
= 125°C, SeeNote2 5 25 mV
Output short circuit –30 –45 –55 mA
Oscillator Section
Initial accuracy T
A
=25°C, SeeNote3 50.5 53 55 kHz
Voltage stability V
DD
=12Vto18V 0.2% 1.0%
Temperature stability T
MIN
to T
MAX
,SeeNote2 1% 2.5%
Amplitude RT/CT Pin peak-to-peak 1.9 V
D
i
s
c
h
a
r
g
e
c
u
r
r
e
n
t
T
A
=25°C, RT/CT = 2 V, See Note 4 7.7 8.4 9.0 mA
Discharge current
RT/CT = 2 V, See Note 4 7.2 8.4 9.5 mA
Error Amplifier Section
Feedback input voltage, initial accuracy V
COMP
=2.5V, T
A
=25°C 2.475 2.500 2.525 V
Feedback input voltage, total variation V
COMP
=2.5V, 2.45 2.50 2.55 V
Input bias current V
FB
=5.0V –0.1 –2.0 μA
Open-loop voltage gain (A
VOL
) V
OUT
=2Vto4V 65 90 dB
Unity gain bandwidth SeeNote2 1.0 1.5 MHz
Power supply rejection ratio (PSRR) V
DD
=12Vto18V 60 dB
Output sink current V
FB
=2.7V, V
COMP
=1.1V 2 14 mA
Output source current V
FB
=2.3V, V
COMP
=5V –0.5 –1.0 mA
High-level output voltage (VOH) V
FB
=2.7V, R
LOAD
=15ktoGND 5 6.8 V
Low-level output voltage (VOL) V
FB
=2.7V, R
LOAD
= 15 k to VREF 0.1 1.1 V
Current Sense Section
Gain SeeNote5,6 2.85 3.00 3.15 V/V
Maximum input signal V
FB
<2.4V 0.9 1.0 1.1 V
Power supply rejection ratio (PSRR) VDD = 12 V to 18 V, See Note 2, 5 70 dB
Input bias current –0.1 –2.0 μA
CS to output delay 35 70 ns
COMP to CS offset V
CS
=0V 1.15 V
NOTE: 1. Adjust V
DD
above the start threshold before setting at 15 V.
NOTE: 2. Ensured by design. Not production tested.
NOTE: 3. Output frequencies of the UCC38C41, UCC38C44 and the UCC38C45 are half the oscillator frequency.
NOTE: 4. Oscillator discharge current is measured with R
T
=10kΩ to V
REF.
NOTE: 5. Parameter measured at trip point of latch with V
FB
=0V.
NOTE: 6. Gain is defined as ACS =
ΔV
COM
ΔV
CS
,0V≼ V
CS
≼ 900mV