Datasheet

UCC2897A
SLUS829D -- AUGUST 2008 -- REVISED JULY 2009
9
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DETAILED PIN DESCRIPTIONS (continued)
VREF
The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a high quality
ceramic bypass capacitor (C
VREF
) to GND for noise filtering and to provide compensation to the regulator
circuitry. The recommended C
VREF
value is 0.22-μF and X7R capacitors are recommended. The minimum
bypass capacitor value is 0.022-μF limited by stability considerations of the bias regulator, while the maximum
is approximately 22-μF. The capacitance on VREF and VDD should be in a minimum ratio of 1:10.
The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias
is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC2897A controller.
The VREF bias profile may not be monotonic before VDD reaches 5.0 V.
For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional
Description section of this datasheet.
SYNC
This pin is a bi-directional synchonization terminal. This pin should be left open if not used.
This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator
of the UCC2897A controller. The synchronizing frequency must be higher than the free running frequency of
the onboard oscillator

T
SYNC
< T
SW

. The acceptable minimum pulse width of the synchronization signal is
approximately 50 ns (positive logic), and it should remain shorter than

1 − D
MAX

× T
SYNC
where D
MAX
is set
by R
ON
and R
OFF
. If the pulse width of the synchronization signal stays within these limits, the maximum
operating duty ratio remains valid as defined by the ratio of R
ON
and R
OFF
, and D
MAX
is the same in free running
and in synchronized modes of operation. If the pulse width of the synchronization signal would exceed the

1 − D
MAX

× T
SYNC
limit, the maximum operating duty cycle is defined by the synchronization pulse width.
In the stand-alone mode, the sync pin is driven by the internal oscillator which provides output pulses. The pulse
width from SYNC output does not vary with the duty cycle. That signal can be use to synchronize other PWM
controllers or circuits needing a constant frequency time base.
External capacitance should be minimized on this pin layout. There should be no capacitors connected between
this pin and GND or PGND. For more information on synchronization of the UCC2897A refer to the Functional
Description section of this datasheet.
GND
This pin provides a reference potential for all small signal control and programming circuitry inside the
UCC2897A. Ground layout is critical for correct operation. High current surges from the MOSFET drivers
conduct through PVDD, OUT, AUX, and PGND. To localize these surges, PVDD must be bypassed directly to
PGND. PGND current must be electrically, capacitively, and inductively isolated from GND with only one short
trace connecting PGND to GND, located to best minimize noise into GND.