Datasheet

UCC2897A
SLUS829D -- AUGUST 2008 -- REVISED JULY 2009
5
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ELECTRICAL CHARACTERISTICS
V
DD
=12V
(1)
,1-μF capacitor from VDD to GND, 0.01-μF capacitor from VREF to GND, R
ON
=R
OFF
=75kΩ,R
DEL
=10kΩ,
R
SLOPE
=50kΩ,--40°C ≤ T
A
=T
J
≤ 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT
SYNCHRONIZATION
SYNC input high voltage 3.0 V
SYNC input low voltage 1.6 V
SYNC pull down output current 600 μA
SYNC pull up output current --600 μA
SYNC output pulse width 150 ns
t
DEL
SYNC-to-output delay 50 ns
PWM
D
MAX
Maximum duty cycle 66% 70% 74%
Minimum duty cycle 0%
PWM offset CS = 0 V 0.43 0.50 0.61 V
CURRENT SENSE
V
LVL
Current sense level shift voltage 0.40 0.50 0.60
V
ERR(max)
Maximum voltage error (clamped) 5.0
V
V
CS
Current sense threshold
cycle --by--cycle
0.43 0.48 0.53
V
OUTPUT (OUT AND AUX)
t
R
Rise time C
LOAD
=2nF 19 28
t
F
Fall time C
LOAD
=2nF 14 23
n
s
t
DEL1
Delay time (AUX to OUT) C
LOAD
=2nF, R
DEL
=10kΩ 110
ns
t
DEL2
Delay time (OUT to AUX) C
LOAD
=2nF, R
DEL
=10kΩ 115
I
OUT(src)
Output source current -- 2
A
I
OUT(sink)
Output sink current 2
A
V
OUT(low)
Low-level output voltage I
OUT
= 150 mA 0.4
V
V
OUT(high)
High-level output voltage I
OUT
= --150 mA 11.1
V
(1)
Set VDD above the start threshold before setting at 12 V.
(2)
Maximum pulse width needs to be less than D
MAX
, which is a function of R
ON
and R
OFF
. For more information on D
MAX
, see detailed pin
description for R
OFF
.
t
DEL2
t
DEL1
t
t
OUT
AUX
(P--channel)
50%
50%
50%
50%
Figure 1. O utput Timing Diagram