Datasheet

UCC2897A
SLUS829D -- AUGUST 2008 -- REVISED JULY 2009
21
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APPLICATION INFORMATION: SETUP GUIDE
Note, that t
SS
defines a time interval to reach the maximum current capability of the converter and not the time
required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme
does not allow accurate control over the ramp up time of the output voltage. In addition to the I
SS
and C
SS
values,
the time required to reach the nominal output voltage of the converter is a function of the maximum output
current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to
implement a tightly controlled ramp-up time at the output of the converter, the soft-start must be implemented
using a closed loop technique. Closed loop soft-start c an be implemented with the error amplifier of the voltage
regulation loop when its voltage reference is ramped from 0 V to its final steady state value during the required
t
SS
start up time interval.
Step 3. VDD Bypass Requirements
First, the high-frequency filter capacitor is calculated based on the gate charge parameters of the external
MOSFETs. Assuming that the basic switching frequency ripple should be kept below 0.1-V across C
HF
,itsvalue
can be approximated as:
C
HF
=
Q
G(main)
+ Q
G(aux)
0.1 V
The energy storage requirements are defined primarily by the start up time (t
SS
) and turn-on (approximately
12.7 V) and turn-off (approximately 8 V) thresholds of the controller’s undervoltage lockout circuit monitoring
the VDD pin. In addition, the bias current consumption of the entire primary side control circuit (I
DD
+I
EXT
)must
be known. This power consumption can be estimated as:
P
BIAS
=

I
DD
+ I
EXT
+

Q
G(main)
+ Q
G(aux)
× f
SW


× V
DD
During start up (t
SS
) this power is provided by C
BIAS
while its voltage must remain above the UVLO turn-off
threshold. This relationship c an be expressed as:
P
BIAS
× t
SS
<
1
2
× C
BIAS
×

12.7
2
− 8
2

Rearranging the equation yields the minimum value for C
BIAS
:
C
BIAS
>
2 × P
BIAS
× t
SS

12.7
2
− 8
2

Equation 17 may yeild a big capacitance value that may not be feasible in some applications. In such cases,
an additional energy storage circuit. A s maller footprint may be designed to ease the space demand. Refer to
the Application Note for such a design.
Step 4. Delay Programming
From the power stage design, the required turn-on delay (t
DEL
) of the gate drive signals is defined. The
corresponding R
DEL
resistor value to implement this delay is given by:
R
DEL
= t
DEL1
× 0.91 × 10
11
×

Ω
s

or
R
DEL
= t
DEL2
× 0.91 × 10
11
×

Ω
s

(13)
(14)
(15)
(16)
(17)
(18)