Datasheet

UCC2897A
SLUS829D -- AUGUST 2008 -- REVISED JULY 2009
18
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FUNCTIONAL DESCRIPTION
Synchronization
The UCC2897A has a bi-directional synchronization pin. In the stand-alone operation the SYNC pin is driven
by the internal oscillator of the UCC2897A which provides an approximately 5-V amplitude square wave output.
This signal can be used to synchronize other PWM controllers or circuits needing a constant frequency time
base. The synchronization output of the UCC2897A is generated when the internal timing capacitor reaches
its peak value. Therefore, the synchronization waveform does not coincide with the turn on of the main gate
driver output as it is usually implemented in PWM controllers.
The operation of the oscillator and relevant other waveforms in free running and synchronized mode are shown
in Figure 6.
SYNC
C
T
D
MAX
AUX
OUT
Figure 6. A Synchronization Waveform for SYNC Input, P--Channel
The most critical and unique feature of the oscillator is to limit the maximum operating duty cycle of the converter.
It is achieved by accurately controlling the charge and discharge intervals of the on board timing capacitor. The
maximum on-time of OUT pin, which is also the maximum duty cycle of the active clamp converter is limited
by the charging interval of the timing capacitor. While the capacitor is being reset to its initial voltage level OUT
is guaranteed to be off.
When synchronization is used, the rising edge of the signal terminates the charging period and initiate the
discharge of the timing capacitor. Once the timing capacitor voltage reaches the predefined valley voltage, a
new charge period starts automatically. This method of synchronization leaves the charge and discharge slopes
of the timing waveform unaffected thus maintains the maximum duty cycle o f the converter, independent of the
mode of operation.
Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising edge
of the waveform. This allows the synchronizing pulse width to vary significantly but certain limitations must be
observed. The minimum pulse width should be sufficient to guarantee reliable triggering of the internal oscillator
circuitry, therefore it should be greater than approximately 50 nanoseconds. The other limiting factor is to keep
it shorter than

1 − D
MAX

× T
SYNC
where T
SYNC
is the period of the synchronization frequency.