Datasheet

REF
Delayed
Clock
Signal
3.5 V
DELAB/CD
From Pad
2.5 V
Clock
Bussed Current
From ADS Circuit
0.5 V
ADS
CS
DELCD
DELAB
REF
TO DELAY A
AND DELAY B
BLOCKS
REF
TO DELAY C
AND DELAY D
BLOCKS
75 kΩ
75 kΩ
100 kΩ
100 kΩ
UCC2895-Q1
www.ti.com SLUS783C –MAY 2008–REVISED AUGUST 2012
Figure 2. Adaptive Delay Setting Block Diagram
Figure 3. Delay Block Diagram (One Delay Block Per Outlet)
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