Datasheet

UCC2895-Q1

www.ti.com

SLUS783C –MAY 2008–REVISED AUGUST 2012

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME NO.

ADS 11 I Adaptive delay set. Sets the ratio between the maximum and minimum programmed output delay dead time.

CS 12 I Current-sense input for cycle-by-cycle current limiting and for overcurrent comparator

Oscillator timing capacitor for programming the switching frequency. The oscillator charges CT via a

CT 7 I

programmed current.

Delay programming between complementary outputs. DELAB programs the dead time between switching of

DELAB 9 I

output A and output B.

Delay programming between complementary outputs. DELCD programs the dead time between switching of

DELCD 10 I

output C and output D.

EAOUT 2 I/O Error amplifier output

EAP 20 I Noninverting input to the error amplifier. Keep below 3.6 V for proper operation.

EAN 1 I Inverting input to the error amplifier. Keep below 3.6 V for proper operation.

GND 5 – Ground for all circuits except the output stages

OUTA 18 O

OUTB 17 O

The four outputs are 100-mA CMOS drivers and are optimized to drive FET driver circuits such as the

UCC27424 or gate-drive transformers.

OUTC 14 O

OUTD 13 O

PGND 16 – Output-stage power ground

RAMP 3 I Inverting input of the PWM comparator

5-V ± 1.2% 5-mA voltage reference. For best performance, bypass with a 0.1-μF low-ESR low-ESL capacitor

REF 4 O

to ground. Do not use more than 1 μF of total capacitance on this pin.

RT 8 I Oscillator timing resistor for programming the switching frequency

SS/DISB 19 I Soft start/disable. This pin combines two independent functions.

SYNC 6 I/O Oscillator synchronization. This pin is bidirectional.

VDD 15 I Power-supply input. VDD must be bypassed with a minimum of a 1-μF low-ESR low-ESL capacitor to ground.

Product Folder Link(s): UCC2895-Q1