Datasheet
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EAN
EAOUT
RAMP
REF
GND
SYNC
CT
RT
DELAB
DELCD
EAP
SS/DISB
OUTA
OUTB
PGND
VDD
OUTC
OUTD
CS
ADS
DW PACKAGE
(TOP VIEW)
UCC2895-Q1
SLUS783C –MAY 2008–REVISED AUGUST 2012
www.ti.com
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 125°C SOIC – DW Reel of 2000 UCC2895QDWRQ1 UCC2895Q
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
(1)
T
A
= –40°C to 125°C, all voltage values are with respect to the network ground terminal (unless otherwise noted)
VALUE
V
DD
Supply voltage I
DD
< 10 mA 17 V
I
DD
Supply current 30 mA
I
REF
Reference current 15 mA
I
O
Output current 100 mA
Analog input voltage range EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB –0.3 V to REF + 0.3 V
Drive output voltage range OUTA, OUTB, OUTC, OUTD –0.3 V to VDD + 0.3 V
P
D
Power dissipation T
A
= 25°C 650 mW
T
stg
Storage temperature range –65°C to 150°C
T
J
Junction temperature range –55°C to 150°C
Human-body model (HBM) 800 V
Electrostatic discharge
ESD Machine model (MM) 200 V
protection
Charged-device model (CDM) 2000 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(1)
MIN NOM MAX UNIT
V
DD
Supply voltage 10 16.5 V
10 ×
C
VDD
Supply voltage bypass capacitor
(2)
μF
C
REF
C
REF
Reference bypass capacitor
(3)
0.1 4.7 μF
C
T
Timing capacitor For 500-kHz switching frequency 220 pF
R
T
Timing resistor For 500-kHz switching frequency 82 kΩ
(1) It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a
separate ground plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 should be
located over this ground plane. Any connections associated with these pins to ground should be connected to this ground plane.
(2) The V
DD
capacitor should be a low-ESR, -ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk
capacitor should be located as physically close as possible to the V
DD
pins.
(3) The V
REF
capacitor should be a low-ESR, -ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is
desired for V
REF
, then it should be located near the V
REF
capacitor and connected to the V
REF
pin with a resistor of 51 Ω or greater. The
bulk capacitor on VDD must be a factor of 10 geater than the total V
REF
capacitance.
2 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): UCC2895-Q1