Datasheet

UCC2895-Q1
SLUS783C –MAY 2008–REVISED AUGUST 2012 www.ti.com
Soft Start/Disable (SS/DISB)
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the UVLO threshold. In the case of REF being pulled
below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal MOSFET switch.
If an overcurrent fault is sensed (CS = 2.5 V), a soft stop is initiated. In this mode, SS/DISB sinks a constant
current of 10 × I
RT
. The soft stop continues until SS/DISB falls below 0.5 V. When any of these faults is detected,
all outputs are forced to ground immediately.
NOTE
If SS/DISB is forced below 0.5 V, the pin starts to source current equal to I
RT
. The only
time the device switches into low I
DD
current mode is when the device is in UVLO.
Soft-Start Mode: After a fault or disable condition has passed, VDD is above the start threshold, or SS/DISB
falls below 0.5 V during a soft stop, SS/DISB switches to a soft-start mode. The pin then sources current equal to
I
RT
. A user-selected resistor-and-capacitor combination on SS/DISB determines the soft-start time constant.
NOTE
SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin
voltage during both soft-start, soft-stop, and disable conditions.
Oscillator Synchronization (SYNC)
This pin is bidirectional (see Figure 1). When used as an output, SYNC can be used as a clock, which is the
same as the internal clock of the device. When used as an input, SYNC overrides the internal oscillator of the
device and acts as its clock signal. This bidirectional feature allows synchronization of multiple power supplies.
Also, the SYNC signal internally discharges the C
T
capacitor and any filter capacitors that are present on the
RAMP pin. The internal SYNC circuitry is level-sensitive, with an input-low threshold of 1.9 V and an input-high
threshold of 2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the SYNC
pulse duration.
Chip Supply (VDD)
This is the input pin to the chip. VDD must be bypassed with a minimum of 1-μF low-ESR low-ESL capacitor to
ground.
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