Datasheet

VDD VDD_GOOD VREF VREF_GOOD CLK TMIN RAMP PWM
A
B C
D E F
COMP
Burst Mode at the beginning of
start up until PWM> T
MIN
pulses
2 V
P-P
TMINPWM
SS > 0.5 V, then release COMP, DCM, CS , Outputs A,B,C,D,E and F
Add 0.85 V offset to RAMP No PWM pulses shorter than TMIN except during cycle-by-cycle current limit
4.8-V rise, 4.6-V fall
7.3-V rise, 6.7-V fall
TMIN
UCC28950
www.ti.com SLUSA16B –MARCH 2010–REVISED OCTOBER 2011
Startup Timing Diagram
No output delay shown, COMP-to-RAMP offset not included.
Figure 1.
Figure 2. UCC28950 Timing Diagram
NOTE
There is no pulse on OUTE during burst mode at startup. Two falling edge PWM pulses
are required before enabling the synchronous rectifier outputs.
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