Datasheet

EN
Thermal
Shutdown
5V LDO
+
V
DD
23VDD
UVLO
COMP
V
DD
1VREF
Reference
Generator
V
DD
ON/OFF
7.3 V Rise
6.7 V Fall
+
-
Programmable
Delay AB
22 OUTA
6 DELAB
21 OUTB
14
ADEL
Programmable
Delay CD
20 OUTC
7 DELCD
19 OUTD
Programmable
Delay EF
18 OUTE
8 DELEF
17 OUTF
13 ADELEF
Soft Stat and Enable
with 0.55 V Threshold
5
SS/EN
Light-Load
Efficiency Block
+
4COMP
+
3
2
EA-
EA+
Oscillator
Lower "+" Input
is Dominant
10RT
Ramp
Summing
11RSUM
15CS
CS
Synchronization
Block
16
SYNC
+
+
-
24
GND
CS
12
DCM
9
TMIN
Logic Block
PWM
COMP
Cycle-by-Cycle
I
LIM
2 V
2.8 V
0.8 V
RAMP
CLK
+
1
2
3
4
5
6
7
8
9
10
11
12
UCC28950
DCM
RSUM
RT
TMIN
DELEF
DELCD
DELAB
SS/EN
COMP
EA-
EA+
VREF
24
23
22
21
20
19
18
17
16
15
14
13ADELEF
ADEL
CS
SYNC
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
VDD
GND
R
DCM(hi)
R
DCM
R
CS
R7
R
A(hi)
R
AEF(hi)
R
AEF
R
A
A
B
C
D
E
F
C
VDD
V
DD
SYNC
V
REF
R5
C2
C1
R4
R3
C
REF
R2
R1
V
SENSE
ENABLE
+
-
CT
A
V
DD
B
V
DD
QA
QB
C
V
DD
D
V
DD
QC
QD
QE QF
E F
V
OUT
+
-
V
SENSE
UCC27324 UCC27324
C3
R6
C
SS
R
AB
R
CD
R
EF
R
TMIN
R
T
R
SUM
Voltage Current
Sense
V
REF
V
S
UCC28950
SLUSA16B –MARCH 2010– REVISED OCTOBER 2011 www.ti.com
Functional Block Diagram
Typical Application Diagram
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Product Folder Link(s): UCC28950