Datasheet

UCC28950
www.ti.com SLUSA16B –MARCH 2010–REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS
(1)
(continued)
V
DD
= 12 V, T
A
= T
J
= -40°C to 125°C, C
VDD
= 1 µF, C
REF
= 1 µF, R
AB
= 22.6 kΩ, R
CD
= 22.6 kΩ , R
EF
= 13.3 kΩ, RSUM = 124
kΩ, RMIN = 88.7 kΩ, RT = 59 kΩ connected between RT pin and 5-V voltage supply to set F
SW
= 100 kHz (F
OSC
= 200 kHz)
(unless otherwise noted). All component designations are from the Typical Application Diagram.
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Programmable Delay Time Set Accuracy and Range
(3)(4)(5)(6)(7)
Short delay time set accuracy
T
ABSET1
CS = ADEL = ADELEF = 1.8 V 32 45 56
between OUTA and OUTB
Long delay time set accuracy
T
ABSET2
CS = ADEL = ADELEF = 0.2 V 216 270 325
between OUTA and OUTB
Short delay time set accuracy
T
CDSET1
CS = ADEL = ADELEF = 1.8 V 32 45 56
between OUTC and OUTD
Long delay time set accuracy
T
CDSET2
CS = ADEL = ADELEF = 0.2 V 216 270 325
between OUTC and OUTD
Short delay time set accuracy
T
AFSET1
CS = ADEL = ADELEF = 0.2 V 22 35 48
between falling OUTA, OUTF
Long delay time set accuracy
T
AFSET2
CS = ADEL = ADELEF = 1.8 V 190 240 290
between falling OUTA, OUTF
Short delay time set accuracy
T
BESET1
CS = ADEL = ADELEF = 0.2 V 22 35 48
between falling OUTB, OUTE
ns
Long delay time set accuracy
T
BESET2
CS = ADEL = ADELEF = 1.8 V 190 240 290
between falling OUTB, OUTE
Pulse matching between
ΔT
ADBC
OUTA rise, OUTD fall and CS = ADEL = ADELEF = 1.8 V, COMP = 2 V -50 0 50
OUTB rise, OUTC fall
Half cycle matching between
ΔT
ABBA
OUTA rise, OUTB rise and CS = ADEL = ADELEF = 1.8 V, COMP = 2 V -50 0 50
OUTB rise, OUTA rise
Pulse matching between
ΔT
EEFF
OUTE fall, OUTE rise and CS = ADEL = ADELEF = 0.2 V, COMP = 2 V -60 0 60
OUTF fall, OUTF rise
Pulse matching between
ΔT
EFFE
OUTE fall, OUTF rise and CS = ADEL = ADELEF = 0.2 V, COMP = 2 V -60 0 60
OUTF fall, OUTE rise
(3) See Figure 4 for timing diagram and T
ABSET1
, T
ABSET2
, T
CDSET1
, T
CDSET2
definitions.
(4) See Figure 7 for timing diagram and T
AFSET1
, T
AFSET2
, T
BESET1
, T
BESET2
definitions.
(5) Pair of outputs OUTC, OUTE and OUTD, OUTF always going high simultaneously.
(6) Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high.
(7) All delay settings are measured relatively 50% of pulse amplitude.
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