Datasheet

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UCC28950
DCM
RSUM
RT
TMIN
DELEF
DELCD
DELAB
SS/EN
COMP
EA-
EA+
VREF
24
23
22
21
20
19
18
17
16
15
14
13ADELEF
ADEL
CS
SYNC
OUTF
OUTE
OUTD
OUTC
OUTB
OUTA
VDD
GND
R
DCM
R
CS
R7
R
A(hi)
A
B
C
D
E
F
VDD
SYNC
VREF
R5
C2
C1
R4
R3
C
REF
R2R1
V
SENSE
ENABLE
Current Sense
Analog
Plane
Power
Plane
R
AEF(hi)
R
A
R
AEF
R
DCM(hi)
C
SS
R
AB
R
CD
R
EF
R
T(min)
R
T
R
SUM)
C
VDD
C3
R6
UCC28950
SLUSA16B –MARCH 2010– REVISED OCTOBER 2011 www.ti.com
Supply Voltage (VDD)
Connect this pin to bias supply from 8 V to 17 V range. Place high quality, low ESR and ESL, at least 1-µF
ceramic bypass capacitor C
VDD
from this pin to GND. It is recommended to use 10-Ω resistor in series to VDD
pin to form RC filter with C
VDD
capacitor.
Ground (GND)
All signals are referenced to this node. It is recommended to have a separate quite analog plane connected in
one place to the power plane. The analog plane combines the components related to the pins VREF, EA+, EA-,
COMP, SS/EN, DELAB, DELCD, DELEF, TMIN, RT, RSUM. The power plane combines the components related
to the pins DCM, ADELEF, ADEL, CS, SYNC, OUTF, OUTE, OUTD, OUTC, OUTB, OUTA, and VDD. An
example of layout and ground planes connection is shown in Figure 22.
Figure 22. Layout Recommendation for Analog and Power Planes
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