Datasheet

OUTA
(OUTB)
OUTD
(OUTC)
OUTF
(OUTE)
T
AFSET1
T
AFSET2
T
BESET2
T
BESET1
EF
AFSET
EF
5 R
T ns 4ns
2.65 V CS K 1.32
æ ö
æ ö
´
= +
ç ÷
ç ÷
ç ÷
- ´ ´
è ø
è ø
AEF
EF
AEF AEF(hi)
R
K
R R
=
+
UCC28950
SLUSA16B –MARCH 2010– REVISED OCTOBER 2011 www.ti.com
Adaptive Delay (Delay between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF))
The resistor R
EF
from the DELEF pin to GND along with the resistor divider R
AEFHI
from CS pin to ADELEF pin
and R
AEF
from ADELEF pin to GND sets equal delays T
AFSET
and T
BESET
between outputs OUTA or OUTB going
low and related output OUTF or OUTE going low Figure 7.
Figure 7. Delay Definitions Between OUTA and OUTF, OUTB and OUTE
These delays gradually increase as function of CS signal from T
AFSET1
, which is measured at V
CS
= 0.2 V, to
T
AFSET2
, which is measured at V
CS
= 1.8 V. Opposite to the DELAB and DELCD behaviour, this delay is longest
(T
AFSET2
) when the signal at CS pin is maximized and shortest (T
AFSET1
) when the CS signal is minimized. This
approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current
range thus improving efficiency and reducing diode recovery time. Depending on the resistor divider R
AEFHI
and
R
AEF
, the proportional ratio between longest and shortest delay is set. If CS and ADELEF are tied, the ratio is
maximized. If ADELEF is connected to GND, then the delay is fixed, defined only by resistor R
EF
from DELEF to
GND.
The delay time T
AFSET
is defined by the following Equation 6. The same defines the delay time T
BESET
.
(6)
In this equation R
EF
is in kΩ, the CS, which is the voltage at pin CS, is in volts and K
EF
is a numerical gain factor
of CS voltage from 0 to 1. The delay time T
AFSET
is in ns. This equation is empirical approximation of measured
data, thus, there is no unit agreement in it. As an example of calculation, assume R
EF
= 15 kΩ, CS = 1 V and K
EF
= 0.5. Then the T
AFSET
is going to be 41.7 ns. K
EF
is defined as:
(7)
R
AEF
and R
AEFHI
define the portion of voltage at pin CS applied to the pin ADELEF (See Typical Application
Diagram ). K
EF
defines how significantly the delay time depends on CS voltage. K
EF
varies from 0, where
ADELEF pin is shorted to ground (R
AEF
= 0) and the delay does not depend on CS voltage, to 1, where ADELEF
is tied to CS (R
AEFHI
= 0).
NOTE
The allowed resistor range on DELEF, R
EF
is 13 kΩ to 90 kΩ.
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