Datasheet

0.0 2.0
CS Voltage - V
350
1.0
T
ABSET
, T
CDSET
- Time Delay - ns
TIME DELAY (R
AB
= R
CD
= 13 kW)
vs
CS VOLTAGE
300
100
5
250
150
50
200
0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8
K
A
= 0.0
K
A
= 0.1
K
A
= 0.25
K
A
= 0.50
K
A
= 0.75
K
A
= 1.0
0.0 2.0
CS Voltage - V
2000
1.0
T
ABSET
, T
CDSET
- Time Delay - ns
TIME DELAY (R
AB
= R
CD
= 90 kW)
vs
CS VOLTAGE
1800
600
0
1600
1000
200
1200
0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8
K
A
= 0.0
K
A
= 0.1
K
A
= 0.25
K
A
= 0.50
K
A
= 0.75
K
A
= 1.0
1400
800
400
UCC28950
www.ti.com SLUSA16B –MARCH 2010–REVISED OCTOBER 2011
R
A
and R
AHI
define the portion of voltage at pin CS applied to the pin ADEL (See Typical Application Diagram).
K
A
defines how significantly the delay time depends on CS voltage. Ka varies from 0, where ADEL pin is shorted
to ground (R
A
= 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (R
AH
= 0).
Setting K
A
, R
AB
and R
CD
provides the ability to maintain optimal ZVS conditions of primary switches over load
current because the voltage at CS pin includes reflected load current to primary side through the current sensing
circuit. The plots in Figure 5 and Figure 6 show the delay time settings as a function of CS voltage and K
A
for two
different conditions: R
AB
= R
CD
= 13 kΩ (Figure 5) and R
AB
= R
CD
= 90 kΩ (Figure 6 ).
Figure 5. Delay Time Set T
ABSET
and T
CDSET
(Over CS voltage variation and selected K
A
for R
AB
and R
CD
equal 13 kΩ)
Figure 6. Delay time set T
ABSET
and T
CDSET
(Over CS voltage variation and selected K
A
for R
AB
and R
CD
equal 90 kΩ)
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