Datasheet

VDD
VDD_GOOD
VREF
VREF_GOOD
CLK
TMIN
No PWM pulses shorter than TMIN except
during cycle-by-cycle current limit
A
B
C
D
E
F
7.3V rise, 6.7V fall
4.8V rise, 4.6V fall
TMIN
VDD failed and VDD_GOOD goes low,
Everything is shutdown
RAMP
2Vp-p
COMP
PWM
Add 0.85V offset to RAMP
UCC28950
SLUSA16B –MARCH 2010– REVISED OCTOBER 2011 www.ti.com
Steady State/Shutdown Timing Diagram
No output delay shown, COMP-to-RAMP offset not included.
Figure 3. UCC28950 Timing Diagram
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Product Folder Link(s): UCC28950