Datasheet

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009
13
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FUNCTIONAL DESCRIPTION
JFET Control and UVLO
The UCC2891 and UCC2893 controllers include a high voltage JFET start up transistor. The steady state power
consumption of the of the control circuit which also includes the gate drive power loss of the two power switches
of an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should
only be used for initial start up of the control circuitry and to provide keep-alive power during stand-by mode
when the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own control
algorithm implemented on board the UCC2891 and UCC2893. The following timing diagram illustrates the
operation of the JFET start up device.
UDG−03148
V
IN
SS/SD
OUTPUTs
ENABLE
(See diagram on p.6)
V
DD
V
ON
Bootstrap bias
OFF SWITCHING OFFOFF
SWITCHING
JFET
OFF OFFOFF
13.5V
10.0V
8.0V
8V <VDD < 10V
Figure 2. JFET Control Startup and Shutdown
During initial power up the JFET is on and charges the C
BIAS
and C
HF
capacitors connected to the VDD pin (pin
14). The VDD pin is monitored by the controller’s undervoltage lockout circuit to ensure proper biasing before
the operation is enabled. When the VDD voltage reaches approximately 12.7 V (UVLO turn-on threshold) the
UVLO circuit enables the rest of the controller. At that time, the JFET is turned off and 5 V appears on the VREF
terminal (pin 4). Switching waveforms might not appear at the gate drive outputs unless all other conditions of
proper operation are met. These conditions are:
D sufficient voltage on the VREF pin (V
VREF
> 4.5V)
D the voltage on the CS pin is below the current limit threshold
D the control voltage is above the zero duty cycle boundary (V
FB
> 1.25 V)
D the input voltage is in the valid operating range (V
VON
<V
VIN
<V
VOFF
) i.e. the line under or overvoltage
protections are not activated.