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Schematic

4 Schematic

A schematic of the UCC2891EVM-520 is shown in Figure 1. Terminal block J1 is the 48-V input voltage-

source connector and J8 is the output and return for the 3.3-V output voltage.

On the primary side, U1 is the UCC2891 shown with the necessary discrete circuitry for configuring the

controller to operate at 300 kHz with the maximum duty clamp set for 0.65. The EVM is programmed to

start at VIN = 36 V, as determined by R11 and R12. To minimize power dissipation in the current sense, a

current-sense transformer, T1 is used, as opposed to simply using a sense resistor between the source of

Q2 and power ground. Q2 is the primary switching MOSFET and is selected based upon VDS and low

DS(on)

. Q1 is the AUX (active reset) MOSFET and is selected based upon preferred package only, with

only minor consideration given for R

DS(on)

and Qg. Since the active clamp used in this design is low-side

referenced, Q1 must be a P-channel type MOSFET. The reason for this is further explained in application

note SLUA299 (see Section 10). C9 is the clamp capacitor used to maintain a constant dc voltage. The

input voltage is subtracted from the clamp voltage to allow transformer reset during the active-clamp

period.

High efficiency is achieved using self-driven synchronous rectification on the secondary side. Q3 and Q4

are placed in parallel and make up the forward synchronous rectifier (SR), while the reverse SR is made

up of the parallel combination of Q5, Q7, and Q8. If the duty cycle were limited to 50% then the reverse

SR reduces to only two parallel MOSFETs, but because these devices are operating near 60% duty cycle

during the freewheel-mode, they carry a higher average current than seen by Q3 and Q4. The output

inductor L1 has a coupled secondary, referenced to the primary side, used to provide bootstrapping

voltage to U1. A stable bias for the optocoupler, U2, is provided by the series-pass regulator made up of

D6, Q6 and some associated filtering.

Scope jacks J2 and J3 allow the user to measure the gate-to-source and drain-to-source signals for Q2,

the primary MOSFET. J4 and J5 allow convenient access to the gate-drive signals of each SR on the

secondary side. J6 and J7 are available allowing the option of using a network analyzer to non-invasively

measure the control to output loop-gain and phase.

SLUU407A–June 2010–Revised May 2013 48-V to 3.3-V Forward Converter With Active-Clamp Reset Using the

UCC2891 Active-Clamp Current-Mode PWM Controller

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