Datasheet

UCC28710, UCC28711
UCC28712, UCC28713
UCC28714, UCC28715
SLUSB86 –NOVEMBER 2012 www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, V
VDD
= 25 V, HV = open, R
CBC(NTC)
= open, T
A
= -40°C to 125°C, T
A
= T
J
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HIGH-VOLTAGE START UP
I
HV
Start-up current out of VDD V
HV
= 100 V, V
VDD
= 0 V, start state 100 250 500
µA
I
HVLKG
Leakage current at HV V
HV
= 400 V, run state 0.1 1
BIAS SUPPLY INPUT
I
RUN
Supply current, run I
DRV
= 0, run state 2.00 2.65 mA
I
WAIT
Supply current, wait I
DRV
= 0, wait state 95 120
I
START
Supply current, start I
DRV
= 0, V
VDD
= 18 V, start state, I
HV
= 0 18 30 µA
I
FAULT
Supply current, fault I
DRV
= 0, fault state 95 125
UNDERVOLTAGE LOCKOUT
V
VDD(on)
VDD turn-on threshold V
VDD
low to high 19 21 23
V
V
VDD(off)
VDD turn-off threshold V
VDD
high to low 7.7 8.1 8.5
VS INPUT
V
VSR
Regulating level Measured at no-load condition, T
J
= 25°C
(1)
4.01 4.05 4.09 V
V
VSNC
Negative clamp level I
VS
= -300 µA, volts below ground 190 250 325 mV
I
VSB
Input bias current V
VS
= 4 V -0.25 0 0.25 µA
CS INPUT
V
CST(max)
Max CS threshold voltage V
VS
= 3.7 V 738 780 810
mV
V
CST(min)
Min CS threshold voltage V
VS
= 4.35 V 175 195 215
K
AM
AM control ratio V
CST(max)
/ V
CST(min)
3.6 4.0 4.4 V/V
V
CCR
Constant current regulating level CC regulation constant 318 330 343 mV
K
LC
Line compensation current ratio I
VSLS
= -300 µA, I
VSLS
/ current out of CS pin 24.0 25.0 28.6 A/A
T
CSLEB
Leading-edge blanking time DRV output duration, V
CS
= 1 V 180 235 280 ns
DRIVERS
I
DRS
DRV source current V
DRV
= 8 V, V
VDD
= 9 V 20 25 mA
R
DRVLS
DRV low-side drive resistance I
DRV
= 10 mA 6 12 Ω
V
DRCL
DRV clamp voltage V
VDD
= 35 V 14 16 V
R
DRVSS
DRV pull-down in start state 150 190 230 kΩ
TIMING
f
SW(max)
Maximum switching frequency V
VS
= 3.7 V 92 100 106 kHz
UCC28710
UCC28711
V
VS
= 4.35 V 600 680 755
UCC28712
f
SW(min)
Minimum switching frequency Hz
UCC28713
V
VS
= 4.35 V UCC28714 340
V
VS
= 4.35 V UCC28715 1500
t
ZTO
Zero-crossing timeout delay 1.80 2.10 2.55 µs
(1) The regulating level at VS decreases with temperature by 0.8 mV/˚C. This compensation is included to reduce the power supply output
voltage variance over temperature.
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