Datasheet
UCC28700, UCC28701
UCC28702, UCC28703
SLUSB41 – JULY 2012
www.ti.com
Detailed Pin Description
VDD (Device Bias Voltage Supply): The VDD pin is connected to a bypass capacitor to ground and a start-up
resistance to the input bulk capacitor (+) terminal. The VDD turn-on UVLO threshold is 21 V and turn-off UVLO
threshold is 8.1 V, with an available operating range up to 35 V. The USB charging specification requires the
output current to operate in constant-current mode from 5 V to a minimum of 2 V; this is easily achieved with a
nominal VDD of approximately 25 V. The additional VDD headroom up to 35 V allows for VDD to rise due to the
leakage energy delivered to the VDD capacitor in high-load conditions. Also, the wide VDD range provides the
advantage of selecting a relatively small VDD capacitor and high-value start-up resistance to minimize no-load
stand-by power loss in the start-up resistor.
GND (Ground): This is a single ground reference external to the device for the gate drive current and analog
signal reference. Place the VDD bypass capacitor close to GND and VDD with short traces to minimize noise on
the VS and CS signal pins.
VS (Voltage-Sense): The VS pin is connected to a resistor divider from the auxiliary winding to ground. The
output-voltage feedback information is sampled at the end of the transformer secondary current demagnetization
time to provide an accurate representation of the output voltage. Timing information to achieve valley-switching
and to control the duty cycle of the secondary transformer current is determined by the waveform on the VS pin.
Avoid placing a filter capacitor on this input which would interfere with accurate sensing of this waveform.
The VS pin also senses the bulk capacitor voltage to provide for AC-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. This information is sensed during the
MOSFET on-time. For the AC-input run/stop function, the run threshold on VS is 220 µA and the stop threshold
is 80 µA. The values for the auxilliary voltage divider upper-resistor R
S1
and lower-resistor R
S2
can be
determined by the equations below.
where
• N
PA
is the transformer primary-to-auxiliary turns ratio,
• V
IN(run)
is the AC RMS voltage to enable turn-on of the controller (run),
• I
VSL(run)
is the run-threshold for the current pulled out of the VS pin during the MOSFET on-time. (see
ELECTRICAL CHARACTERISTICS) (1)
where
• V
OCV
is the converter regulated output voltage,
• V
F
is the output rectifier forward drop at near-zero current,
• N
AS
is the transformer auxiliary to secondary turns ratio,
• R
S1
is the VS divider high-side resistance,
• V
VSR
is the CV regulating level at the VS input (see ELECTRICAL CHARACTERISTICS). (2)
DRV (Gate Drive): The DRV pin is connected to the MOSFET gate pin, usually through a series resistor. The
gate driver provides a gate-drive signal limited to 14 V. The turn-on characteristic of the driver is a 25-mA current
source which limits the turn-on dv/dt of the MOSFET drain and reduces the leading-edge current spike, but still
provides gate-drive current to overcome the Miller plateau. The gate-drive turn-off current is determined by the
low-side driver R
DS(on)
and any external gate-drive resistance. The user can reduce the turn-off MOSFET drain
dv/dt by adding external gate resistance.
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