Datasheet
UCC28610
www.ti.com
SLUS888F –JANUARY 2009–REVISED SEPTEMBER 2012
ABSOLUTE MAXIMUM RATINGS
(1)
All voltages are with respect to GND, –40°C < T
J
= T
A
< 125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted)
UCC28610 UNIT
VDD –0.5 to +25
DRV, during conduction –0.5 to +2.0
DRV, during non-conduction 20
Input voltage range VGG
(2)
–0.5 to +16 V
ZCD, MOT, CL
(3)
–0.5 to +7
FB
(3)
–0.5 to +1.0
VDD – VGG –7 to +10
Continuous input current I
VGG
(2)
10
mA
Input current range I
ZCD
, I
MOT
, I
CL
, I
FB
(3)
–3 to +1
DRV -5
Peak output current A
DRV, pulsed 200ns, 2% duty cycle –5 to +1.5
T
J
Operating junction temperature range –40 to +150
T
stg
Storage temperature range –65 to +150 °C
Lead Temperature (soldering, 10 sec.) +260
HBM ESD Rating, Human Body Model 1.5 kV
CDM ESD Rating, Charged Device Model 500 V
(1) These are stress ratings only. Stress beyond these limits may cause permanent damage to the device. Functional operation of the
device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability
(2) Voltage on VGG is internally clamped. The clamp level varies with operating conditions. In normal use, VGG is current fed with the
voltage internally limited
(3) In normal use, MOT, CL, ZCD, and FB are connected to resistors to GND and internally limited in voltage swing
THERMAL INFORMATION
UCC28610
THERMAL METRIC SOIC (D) PDIP (P)
(1)
UNITS
8 PINS 8 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
117.5 56.3
θ
JCtop
Junction-to-case (top) thermal resistance
(3)
63.7 45.7
θ
JB
Junction-to-board thermal resistance
(4)
57.8 33.5 °C/W
ψ
JT
Junction-to-top characterization parameter
(5)
15.3 22.9
ψ
JB
Junction-to-board characterization parameter
(6)
57.3 33.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: UCC28610