Datasheet

   
   
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
8
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block diagram
UDG−98189
VREF20
14
12
11
9
4
17 16
GT1
PWRGND
ISENSE1
VCC
OVP/ENBL
VAOUT
1.9 V
PKLMT
7.5 V
REFERENCE
UVLO
16 V/10 V
10.5 V/10 V
VCC
15
OSCILLATOR
2
RT
5
CT
S
Q
R
PWM
LATCH
CAOUT
SS2
VOLTAGE
ERROR AMP
8.0 V
13
1
3
VSENSE
VFF
19
IAC
18
MOUT
MIRROR
2:1
7.5 V
ENABLE
PFCOVP
÷
X
X
MULT
CLK1
CURRENT
AMP
6.75 V
6
GND
10
GT2
VCC
7
8
CLK2
1.5 V
R
I
LIMIT
CLK2
OSC
CLK1
CLK2
VERR
ISENSE2
I
LIMIT
S
Q
UVLO2
PWM
0.33 V
(V
FF
)
2
ZERO
POWER
SECOND STAGE
SOFT START
+
+
PWM
+
+
+
+
+
+
+
+
4.5 V
PWM 2ND STAGE
SECTION
PFC SECTION
PWM 2ND STAGE
SECTION
PFC SECTION
1.3 V
R
R