Datasheet

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SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
17
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TYPICAL APPLICATION
The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed
forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant and
to providing input power limiting. Please refer to Texas instruments Application Note on Power Limiting with
Sinusoidal Input TI Literature No. SLUA196, for detailed explanation on how the VFF pin provides power
limiting. The following equation is used to determine the VFF resistor size (R
VFF
) to provide power limiting where
V
IN(min)
is the minimum RMS input voltage and R
IAC
is the total resistance connected between the IAC pin and
the rectified line voltage.
R
VFF
+
1.4 V
ǒ
V
IN (min)
0.9
2 R
IAC
Ǔ
^ 28.7 kW
Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total
harmonic distortion caused by the 120-Hz rectified line voltage. Refer to Unitrode Power Supply Design
Seminar, SEM−700 Topic 7, Optimizing a High Power Factor Switching Preregulator, TI Literature No.
SLUP093. A single pole filter is adequate for this design. Assuming that an allocation of 1.5% total harmonic
distortion from this input is allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the
amount of attenuation required by this filter is:
1.5%
66%
+ 0.022
With a ripple frequency (f
R
) of 120-Hz and an attenuation of 0.022 requires that the pole of the filter (f
P
) be placed
at:
f
P
+ 120 Hz 0.022 ^ 2.6 Hz
The following equation is used to select the filter capacitor (C
VFF
) required to produce the desired low pass filter.
C
VFF
+
1
2p R
VFF
f
P
^ 2.2 mF
This results in a single-pole filter, which adequately attenuates the harmonic distortion and provides power
limiting.
The R
MOUT
resistor is sized to provide power limiting for the circuit. The power limit is set to 140% of the
maximum output power. This is done so that the power limit of the PFC stage does not interfere with power
limiting of the dc-to-dc converter, which is set to 130% of the maximum output power. The following equations
are used to size the R
MOUT
resistor, R19. In these equations P
LIMIT
is the power limit level, P
OUT
is the maximum
output power. I
MOUT(max)
is the maximum multiplier output current, I
IAC
@V
IN(min)
is the minimum current into
the IAC pin at low line and V
VAOUT(max)
is the maximum voltage amplifier output voltage. For this design R19
and R15 need to be approximately 3.57 kΩ.
P
LIMIT
+
P
OUT
1.4
h1 h2
I
MOUT(max)
+
I
IAC
@V
IN(min)
ǒ
V
VAOUT(max)
* 1V
Ǔ
K
ǒ
V
FF
Ǔ
2
(12)
(13)
(14)
(15)
(16)
(17)