Datasheet

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ
LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR
SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
UCC384 short-circuit timing (continued)
During an overcurrent condition, the regulator actively limits the maximum output current to the peak-current
limit. This limits the output voltage of the regulator to:
V
OUT
+ I
PEAK
R
L
(1)
If the output current stays above the overcurrent threshold, the voltage on the SD/CT pin reaches –2.6 V with
respect to GND and the output turns off. The CT capacitor is then discharged by a 1-µA current source. When
the voltage on the SD/CT pin reaches –1.6 V with respect to GND, the output turns back on. This process repeats
until the output current falls below the overcurrent threshold.
t
ON
, the time the output is on during an overcurrent condition is determined by the following equation:
t
ON
+ CT
(
mF
)
1V
40 mA
seconds
(2)
t
OFF
, the time the output is off during an overcurrent condition is determined by the following equation:
t
OFF
+ CT
(
mF
)
1V
1 mA
seconds
(3)
capacitive loads
A capacitive load on the regulator’s output appears as a short-circuit during start-up. If the capacitance is too
large, the output voltage does not begin to regulate during the initial t
ON
period and the UCC384 enters a pulsed
mode operation. For a constant current load the maximum allowed output capacitance is calculated as follows:
C
OUT(max)
+
ƪ
I
PEAK
(A) * I
LOAD
(A)
ƫ
t
ON
(sec)
V
OUT
(V)
Farads
(4)
For worst case calculations, the minimum value for t
ON
should be used, which is based on the value of CT
capacitor selected. For a resistive load the maximum output capacitor can be estimated as follows:
C
OUT(max)
+
t
ON
(sec)
R
LOAD
(W) ȏn
ȧ
ȧ
ȧ
ȡ
Ȣ
1
1
*
ǒ
V
OUT
(V)
I
MAX
(A) R
LOAD
(W)
Ǔ
ȧ
ȧ
ȧ
ȣ
Ȥ
Farads
(5)
Figure 6 and Figure 7 are oscilloscope photos of the UCC384–ADJ operating during an overcurrent condition.
Figure 6 shows operation of the circuit as the output current initially rises above the overcurrent threshold. This
is shown on a 1ms/div. scale. Figure 7 shows operation of the same circuit on a 25 ms/div. scale showing one
complete cycle of operation during an overcurrent condition.